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NANO130_H2Press/User/spi_FRam.c

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初始版本提交
2025-04-10 14:54:41 +08:00
/*
*********************************************************************************************************
* IAR Development Kits
* on the
*
* M451
*
* Filename : spi_fram.c
* Version : V1.00
* Programmer(s) : Qian Xianghong
*********************************************************************************************************
*/
#include "includes.h"
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define FRAM_OP_WREN 0x06 // Set write enable latch
#define FRAM_OP_WRDI 0x04 // Reset write enable latch
#define FRAM_OP_RDSR 0x05 // Read Status Register
#define FRAM_OP_WRSR 0x01 // Write Status Register
#define FRAM_OP_READ 0x03 // Read memory data
#define FRAM_OP_FSTRD 0x0B // Fast read memory data
#define FRAM_OP_WRITE 0x02 // Write memory data
#define FRAM_OP_SLEEP 0xB9 // Enter sleep mode
#define FRAM_OP_RDID 0x9F // Read device ID
// <20><><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>SR)д<><D0B4><EFBFBD><EFBFBD>(WEL)<29><>־λ
#define FRAM_WEL_Pos 1
#define FRAM_WEL_Msk (0x01 << FRAM_WEL_Pos)
void FRAM_Init()
{
/* Set SPI0 multi-function pins */
/* Set SPI1 multi-function pins */
SYS->PE_L_MFP &= ~(SYS_PE_L_MFP_PE1_MFP_Msk | SYS_PE_L_MFP_PE2_MFP_Msk | SYS_PE_L_MFP_PE3_MFP_Msk | SYS_PE_L_MFP_PE4_MFP_Msk);
SYS->PE_L_MFP |= (SYS_PE_L_MFP_PE1_MFP_SPI0_SS0 | SYS_PE_L_MFP_PE2_MFP_SPI0_SCLK | SYS_PE_L_MFP_PE3_MFP_SPI0_MISO0 | SYS_PE_L_MFP_PE4_MFP_SPI0_MOSI0);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
CLK_EnableModuleClock(SPI0_MODULE);
}
void FRAM_Open()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init SPI */
/*---------------------------------------------------------------------------------------------------------*/
/* Configure SPI0 as a master, SPI clock rate 36 MHz,
clock idle low, 8-bit transaction, drive output on falling clock edge and latch input on rising edge. */
SPI_Open(SPI0, SPI_MASTER, SPI_MODE_0, 8, 36000000ul);
/* Disable the automatic hardware slave selection function. */
SPI_DisableAutoSS(SPI0);
SPI_SET_MSB_FIRST(SPI0);
/* Set TX FIFO threshold, enable TX FIFO threshold interrupt and RX FIFO time-out interrupt */
SPI_EnableFIFO(SPI0, 1, 1);
}
void FRAM_ReadID()
{
uint8_t i;
SPI_SET_SS0_LOW(SPI0);
SPI_WRITE_TX0(SPI0, FRAM_OP_RDID);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
printf("\nFRAM ID is: ");
for(i = 0; i < 9; i++)
{
SPI_WRITE_TX0(SPI0, 0); // <20>ṩCLK
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
printf(" %02X", SPI_READ_RX0(SPI0));
}
printf("\n");
SPI_SET_SS0_HIGH(SPI0);
}
uint8_t FRAM_WriteEN()
{
uint8_t SR = 0x00;
SPI_SET_SS0_LOW(SPI0);
// Write Enabled
SPI_WRITE_TX0(SPI0, FRAM_OP_WREN);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
SPI_SET_SS0_HIGH(SPI0);
// Read SR
SPI_SET_SS0_LOW(SPI0);
SPI_WRITE_TX0(SPI0, FRAM_OP_RDSR);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
SPI_WRITE_TX0(SPI0, 0); // <20>ṩCLK
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SR = SPI_READ_RX0(SPI0);
SPI_SET_SS0_HIGH(SPI0);
// Check WEL
if(SR & FRAM_WEL_Msk)
return 1;
printf("\nFRam write enable failed\n");
return 0;
}
uint8_t FRAM_WriteDI()
{
uint8_t SR = 0xFF;
SPI_SET_SS0_LOW(SPI0);
// Write Enabled
SPI_WRITE_TX0(SPI0, FRAM_OP_WRDI);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
SPI_SET_SS0_HIGH(SPI0);
// Read SR
SPI_SET_SS0_LOW(SPI0);
SPI_WRITE_TX0(SPI0, FRAM_OP_RDSR);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
SPI_WRITE_TX0(SPI0, 0); // <20>ṩCLK
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SR = SPI_READ_RX0(SPI0);
SPI_SET_SS0_HIGH(SPI0);
// Check WEL
if(SR & FRAM_WEL_Msk)
{
printf("\nWrite disable failed\n");
return 0;
}
return 1;
}
uint16_t FRAM_BufferWrite(uint32_t Addr, uint8_t *buf, uint32_t nbytes)
{
uint16_t i;
__disable_irq();
FRAM_WriteEN();
SPI_SET_SS0_LOW(SPI0);
// Write
SPI_WRITE_TX0(SPI0, FRAM_OP_WRITE);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// address high byte
SPI_WRITE_TX0(SPI0, Addr >> 8);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// address low byte
SPI_WRITE_TX0(SPI0, Addr & 0xFF);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// data
for(i = 0; i < nbytes && Addr + i < FRAM_SIZE; i++)
{
SPI_WRITE_TX0(SPI0, buf[i]);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
}
SPI_SET_SS0_HIGH(SPI0);
__enable_irq();
return i;
}
uint16_t FRAM_BufferRead(uint32_t Addr, uint8_t *buf, uint32_t nbytes)
{
uint16_t i;
__disable_irq();
SPI_SET_SS0_LOW(SPI0);
// Read
SPI_WRITE_TX0(SPI0, FRAM_OP_READ);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// address high byte
SPI_WRITE_TX0(SPI0, Addr >> 8);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// address low byte
SPI_WRITE_TX0(SPI0, Addr & 0xFF);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// data
for(i = 0; i < nbytes && Addr + i < FRAM_SIZE; i++)
{
SPI_WRITE_TX0(SPI0, 0); // <20>ṩCLK
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
buf[i] = SPI_READ_RX0(SPI0);
}
SPI_SET_SS0_HIGH(SPI0);
__enable_irq();
return i;
}
uint32_t FRAM_BufferVerify(uint32_t Addr, uint8_t *buf, uint32_t nbytes)
{
uint32_t ret = TRUE;
uint16_t i;
__disable_irq();
SPI_SET_SS0_LOW(SPI0);
// Read
SPI_WRITE_TX0(SPI0, FRAM_OP_READ);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// address high byte
SPI_WRITE_TX0(SPI0, Addr >> 8);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// address low byte
SPI_WRITE_TX0(SPI0, Addr & 0xFF);
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
SPI_READ_RX0(SPI0);
// data
for(i = 0; i < nbytes && Addr + i < FRAM_SIZE; i++)
{
SPI_WRITE_TX0(SPI0, 0); // <20>ṩCLK
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0));
if(buf[i] != SPI_READ_RX0(SPI0))
{
ret = FALSE;
break;
}
}
SPI_SET_SS0_HIGH(SPI0);
__enable_irq();
return ret;
}
void FRAM_Sleep(uint8_t sleep)
{
SPI_SET_SS0_LOW(SPI0);
// Chip erase
if(sleep)
SPI_WRITE_TX0(SPI0, FRAM_OP_SLEEP);
else
SPI_WRITE_TX0(SPI0, 0);
SPI_SET_SS0_HIGH(SPI0);
}
// <20><>FRAM<41><4D>ȡ<EFBFBD><C8A1>¼<EFBFBD><C2BC>ǰ<EFBFBD><C7B0>2<EFBFBD><32><EFBFBD>ֽ<EFBFBD>Ϊ<EFBFBD><CEAA>־0x55AA<41><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>Ϊcrc<72><63>
uint32_t FRAM_LoadInfo(uint32_t Addr, uint8_t *buf, uint32_t nbytes)
{
if(FRAM_BufferRead(Addr, buf, nbytes) == nbytes && Byte2IntS(buf, 0) == 0x55AA && do_crc_16(0, buf, nbytes) == 0)
return 1;
memset(buf, 0, nbytes);
return 0;
}
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC>FRAM<41>У<EFBFBD>ǰ<EFBFBD><C7B0>2<EFBFBD><32><EFBFBD>ֽ<EFBFBD>Ϊ<EFBFBD><CEAA>־0x55AA<41><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>Ϊcrc<72><63>
uint32_t FRAM_SaveInfo(uint32_t Addr, uint8_t *buf, uint32_t nbytes)
{
Int2ByteS(buf, 0, 0x55AA);
Int2ByteS(buf, nbytes - 2, do_crc_16(0, buf, nbytes - 2));
return (FRAM_BufferWrite(Addr, buf, nbytes) == nbytes);
}
// ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD>ֲ<EFBFBD><D6B2><EFBFBD>
// <20><>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>дָ<D0B4><D6B8><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˷<EFBFBD><CBB7><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݿռ䣩<D5BC><E4A3A9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݿռ<DDBF>
void LoopBuff_Create(loopbuff_t *lpbuf, uint16_t itemSize, uint16_t maxItemCount, uint32_t info_base, uint32_t data_base)
{
memset(&lpbuf->info, 0, sizeof(loopbuff_info_t));
lpbuf->itemSize = itemSize;
lpbuf->maxItemCount = maxItemCount;
lpbuf->info_base = info_base;
// if(info_base == 0) // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>չ<EFBFBD>ڴ<EFBFBD>
// lpbuf->data = SRAM_Alloc(itemSize * (maxItemCount + 1));
// else // <20><>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ<CFB5>ڴ<EFBFBD>λ<EFBFBD><CEBB>
lpbuf->data_base = data_base;
}
void LoopBuff_Clear(loopbuff_t *lpbuf)
{
lpbuf->info.rdPtr = lpbuf->info.wtPtr;
}
uint16_t LoopBuff_GetCount(loopbuff_t *lpbuf)
{
if(lpbuf->info.rdPtr <= lpbuf->info.wtPtr)
return lpbuf->info.wtPtr - lpbuf->info.rdPtr;
return (lpbuf->maxItemCount + 1) - lpbuf->info.rdPtr + lpbuf->info.wtPtr;
}
uint16_t LoopBuff_GetNextPtr(loopbuff_t *lpbuf, uint16_t ptr)
{
if(ptr == lpbuf->maxItemCount)
return 0;
return (ptr + 1);
}
void LoopBuff_PutItem(loopbuff_t *lpbuf, uint8_t *item)
{
uint16_t nextPtr;
// <20>ƶ<EFBFBD>дָ<D0B4><D6B8>
nextPtr = LoopBuff_GetNextPtr(lpbuf, lpbuf->info.wtPtr);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><CEB4>
if(nextPtr != lpbuf->info.rdPtr)
{
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼӵ<DDBC><D3B5><EFBFBD><EFBFBD><EFBFBD>
memmove(lpbuf->data + lpbuf->info.wtPtr * lpbuf->itemSize, item, lpbuf->itemSize);
lpbuf->info.wtPtr = nextPtr;
}
else
{
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
}
void LoopBuff_RemoveItems(loopbuff_t *lpbuf, uint16_t count)
{
while(lpbuf->info.rdPtr != lpbuf->info.wtPtr && count--)
lpbuf->info.rdPtr = LoopBuff_GetNextPtr(lpbuf, lpbuf->info.rdPtr);
}
uint32_t LoopBuff_GetDataPos(loopbuff_t *lpbuf, uint16_t ptr)
{
return lpbuf->data_base + lpbuf->itemSize * ptr;
}
uint8_t *LoopBuff_GetDataPtr(loopbuff_t *lpbuf, uint16_t ptr)
{
return lpbuf->data + lpbuf->itemSize * ptr;
}