/**************************************************************************//**
 * @file     main.c
 * @version  V3.00
 * $Revision: 9 $
 * $Date: 18/09/02 10:04a $
 * @brief    Show how to wake up system from Power-down mode by GPIO interrupt.
 * @note
 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
 ******************************************************************************/
#include "includes.h"

const uint8_t CONFIG_BOARD_SELF = CONFIG_BOARD_SINGLE;

// 启动原因代码
volatile uint32_t SYS_RSTSTS;

// 配置外设引脚、时钟等
static void Modules_Init()
{
	Vcc_Init();
	Clock_Init();	// 配置滴答时钟：1ms
	Console_Init();
	SFlash_Init();
	FRAM_Init();
	Config_Init();
	Wakeup_Init();
	RF_Init();
	BD_Init();	
	Sensor_Init();	
	Sample_Init();
	Battery_Init();
	DTU_Init();
	Key_Init();
	Accelero_Init();
	LCD_Init();
	Watchdog_Init();
}

// 打开外设，配置中断等
static void Modules_Open()
{
	Console_Open();
	SFlash_Open();
	FRAM_Open();
	Config_Open();
	Wakeup_Open();
	RF_Open();
	BD_Open();
	Sensor_Open();	
	Sample_Open();
	Battery_Open();
	DTU_Open();
	Key_Open();
	Accelero_Open();
	LCD_MyOpen();	// form.h
	Watchdog_Open();
}

void SYS_Init(void)
{
    /*---------------------------------------------------------------------------------------------------------*/
    /* Init System Clock                                                                                       */
    /*---------------------------------------------------------------------------------------------------------*/

#if 0
    /* Enable External XTAL (4~24 MHz), enable LXT for LCD */
    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_LIRC_EN_Msk);
    CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, 36000000ul);

    /* Waiting for PLL clock ready */
    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_LIRC_STB_Msk | CLK_CLKSTATUS_PLL_STB_Msk);
	
    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(1));
#else
    /* Enable External XTAL (4~24 MHz), enable LXT for LCD */
    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_LIRC_EN_Msk);

    /* Waiting for 12MHz clock ready */
    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_LIRC_STB_Msk);

    /* Switch HCLK clock source to XTAL */
    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_HCLK_CLK_DIVIDER(1));

    /* Switch HCLK clock source to PLL */
    CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
    CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HXT;
#endif

	/* Update System Core Clock */
    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
    SystemCoreClockUpdate();

	Modules_Init();
}

/*---------------------------------------------------------------------------------------------------------*/
/* MAIN function                                                                                           */
/*---------------------------------------------------------------------------------------------------------*/
const uint8_t MEMORY_BYTE[] = {0x55, 0xAA, 0xCC, 0x33, 0xFF, 0x00};
int main(void)
{
	uint32_t i, j, k;
	uint8_t *sram = (uint8_t *) 0x60000000ul;
	
    /* Unlock protected registers */
    SYS_UnlockReg();

	SYS_RSTSTS = SYS->RST_SRC & 0xB7;
	if(SYS_RSTSTS & SYS_RST_SRC_RSTS_POR_Msk)		// 1
		SYS->RST_SRC |= SYS_RST_SRC_RSTS_POR_Msk;
	if(SYS_RSTSTS & SYS_RST_SRC_RSTS_PAD_Msk)		// 2
		SYS->RST_SRC |= SYS_RST_SRC_RSTS_PAD_Msk;
	if(SYS_RSTSTS & SYS_RST_SRC_RSTS_WDT_Msk)		// 4
		SYS->RST_SRC |= SYS_RST_SRC_RSTS_WDT_Msk;
	if(SYS_RSTSTS & SYS_RST_SRC_RSTS_BOD_Msk)		// 16
		SYS->RST_SRC |= SYS_RST_SRC_RSTS_BOD_Msk;
	if(SYS_RSTSTS & SYS_RST_SRC_RSTS_SYS_Msk)		
		SYS->RST_SRC |= SYS_RST_SRC_RSTS_SYS_Msk;	// 32
	if(SYS_RSTSTS & SYS_RST_SRC_RSTS_CPU_Msk)		// 128
		SYS->RST_SRC |= SYS_RST_SRC_RSTS_CPU_Msk;
	
    /* Init System, peripheral clock and multi-function I/O */
    SYS_Init();
	
	Modules_Open();
	
	printf("\nSYS_RSTSTS = %d\n", SYS_RSTSTS);
	
#if 0	
	// SRAM Test
	for(j = 0; j < 6; j++)
	{
		printf("\nSRAM write testing ... 0x%02X\n", MEMORY_BYTE[j]);
		for(i = 0; i < SRAM_SIZE; i++)
			sram[i] = MEMORY_BYTE[j];
		
		printf("\nSRAM read testing ...\n");
		for(i = 0, k = 0; i < SRAM_SIZE; i++)
		{
			if(sram[i] != MEMORY_BYTE[j])
			{
				printf("\nSRAM[%08X] = %02X != %02X\n", i, sram[i], MEMORY_BYTE[j]);
				if(++k >= 10)
					break;
			}
		}
	}
	printf("\nSRAM test finished\n");
#endif	
	SFlash_ReadID();
	FRAM_ReadID();

    /* Lock protected registers */
//    SYS_LockReg();

	HT1621_AllOn();
	delay_ms(1000);
	// 显示主界面
	Form_Start();

	DTU_Task(NULL);
//	while(1)
//	{
//		printf("\n test print ....... \n");
//		delay_ms(500);
//	}
}

uint16_t Byte2IntS(uint8_t *buf, int pos)
{
	return (uint16_t)(buf[pos] | (buf[pos + 1] << 8));
}

void Int2ByteS(uint8_t *buf, int pos, uint16_t val)
{
	buf[pos] = (uint8_t) (val & 0xFF);
	buf[pos + 1] = (uint8_t)((val >> 8) & 0xFF);
}

uint32_t Byte2IntL(uint8_t *buf, int pos)
{
	return (uint32_t)(buf[pos] | (buf[pos + 1] << 8) | (buf[pos + 2] << 16) | (buf[pos + 3] << 24));
}

void Int2ByteL(uint8_t *buf, int pos, uint32_t val)
{
	buf[pos] = (uint8_t)(val & 0xFF);
	buf[pos + 1] = (uint8_t)((val >> 8) & 0xFF);
	buf[pos + 2] = (uint8_t)((val >> 16) & 0xFF);
	buf[pos + 3] = (uint8_t)((val >> 24) & 0xFF);
}

/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/