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ShipCentralControl/RF-AP/RF-Module.c

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增加RF-AP程序
2025-04-07 09:18:02 +08:00
// Haybin_Wu
// Shenitech-RD
// 2016.5
// Built with IAR Embedded Workbench v6.2
//******************************************************************************
// Modify by Qian Xianghong
// 2020.10
// <20>޸<EFBFBD><DEB8><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>ɴ<EFBFBD><C9B4>ں<EFBFBD>RF˫<46><CBAB>͸<EFBFBD><CDB8>ģʽ<C4A3><CABD>
//******************************************************************************
#include <msp430FR2433.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "FR2433-RFSX.h"
#include "RF_SX1276.h"
// <20><>Ƶ<EFBFBD><C6B5><EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
lora_param_t Lora_Param;
#define TRAN_BUF_SIZE (1024)
// <20><>UA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
char printBuf[200];
void uart_print()
{
#if 0 // <20><>ӡ<EFBFBD><D3A1><EFBFBD>ڵ<EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MD0<44><30>MD1ģʽѡ<CABD><D1A1>
char *p = printBuf;
while(*p)
{
if(*p == '\n') // <20><><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ӻس<D3BB>
{
while(!(UCA1IFG & UCTXIFG));
UCA1TXBUF = '\r';
}
while(!(UCA1IFG & UCTXIFG));
UCA1TXBUF = *p++;
}
#endif
}
// <20>ɱ<EFBFBD><C9B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĺ궨<C4BA><EAB6A8>
#define PRINTF(format, ...) \
{ \
snprintf(printBuf, sizeof(printBuf), format, ##__VA_ARGS__); \
uart_print(); \
}
// UA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>buf
uint8_t UA0_RxBuf[TRAN_BUF_SIZE] = {0};
uint16_t UA0_RxBuf_Length = 0;
uint16_t UA0_RxBuf_offset = 0;
// UA0<41><30><EFBFBD>ճ<EFBFBD>ʱ
volatile uint8_t UA0_Rx_Timeout = 1;
// RF<52><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>buf
uint8_t RF_RxBuf[TRAN_BUF_SIZE] = {0};
uint16_t RF_RxBuf_Length = 0;
uint16_t RF_RxBuf_offset = 0;
// RF<52><46><EFBFBD>ճ<EFBFBD>ʱ<EFBFBD><CAB1>־
volatile uint8_t RF_Rx_Timeout = 1;
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD>ڳ<EFBFBD>ʼ<EFBFBD><CABC>
void UA0_Init(uint32_t baudrate)
{
// Configure UART
UCA0CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+
// Baud Rate calculation
if(baudrate == 115200)
{
UCA0BR0 = 4; // 8000000/16/115200//<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>16 UCOS16λҪ<CEBB><D2AA>λ
UCA0BR1 = 0; // Fractional portion = 0.44444
UCA0MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢<><CEA2>Baud Rate
}
else if(baudrate == 38400)
{
UCA0BR0 = 13; // 8000000/16/38400 /<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>16 UCOS16λҪ<CEBB><D2AA>λ
UCA0BR1 = 0; // Fractional portion = 0.33333
UCA0MCTLW = 0x8400 | UCOS16 | UCBRF_0;//΢<><CEA2>Baud Rate
}
else
{
UCA0BR0 = 52; // 8000000/16/9600 /<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>16 UCOS16λҪ<CEBB><D2AA>λ
UCA0BR1 = 0; // Fractional portion = 0.33333
UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1;//΢<><CEA2>Baud Rate
}
UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
}
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void UA0_Response(char *s)
{
while(*s)
{
while(!(UCA0IFG & UCTXIFG));
UCA0TXBUF = *s++;
}
// <20>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>ͽ<EFBFBD><CDBD><EFBFBD>
while(!(UCA0IFG & UCTXCPTIFG));
DelayMs(2);
}
////////////////////////////////////////////////////////////////////////////////
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
////////////////////////////////////////////////////////////////////////////////
int main(void)
{
uint8_t sendCh;
WDTCTL = (WDTPW | WDTHOLD); // Stop WDT
// Port Configuration all un-used pins to output low
P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF;
P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00;
PM5CTL0 &= ~LOCKLPM5;//<2F><><EFBFBD><EFBFBD><EFBFBD>Ź<EFBFBD><C5B9><EFBFBD>
// Configure DCO Clock
//<2F>ⲿʱ<E2B2BF><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>
P2SEL0 |= (BIT0 | BIT1); // set XT1 pin as second function
do
{
CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag
SFRIFG1 &= ~OFIFG;
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD>͹<EFBFBD><CDB9><EFBFBD>
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__XT1CLK; // <20>ⲿ 32768hz reference source
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_3; //DCO=8Mhz
CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
CSCTL4 = SELREF__XT1CLK + SELMS__DCOCLKDIV;// set XT1CLK(32768Hz) as ACLK source & MCLK/SMCLK=DCO
//Timer0_A0 setup
TA0CCTL0 = CCIE; // TACCR0 interrupt enabled
TA0CCR0 = 32768 / 32; // <20><><EFBFBD>ڽ<EFBFBD><DABD>ճ<EFBFBD>ʱ: 1000/32=31.25ms
TA0CTL = MC__STOP | TACLR; // Stop mode, Clear counter
//Timer1_A0 setup
TA1CCTL0 = CCIE; // TACCR0 interrupt enabled
TA1CCR0 = 32768 / 4; // RF<52><46><EFBFBD>ճ<EFBFBD>ʱ: 1000/4=250ms
TA1CTL = MC__STOP | TACLR; // Stop mode, Clear counter
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ȱʡ<C8B1><CAA1><EFBFBD><EFBFBD>
Lora_Param.sof = 0xC2;
Lora_Param.addr = 0xADF2; // ͨ<>ŵ<EFBFBD>ַ0xADF2
Lora_Param.sf = 6; // sf=12
Lora_Param.baud = 3; // 9600
Lora_Param.cr = 0; // cr=4/5
Lora_Param.ch = 9; // 479MHz
Lora_Param.power = 1; // 17dBm
Lora_Param.freqcast = 0; // freqcast off
Lora_Param.bw = 9; // 500kHz
Lora_Param.unicast = 0; // unicast off
// Configure UART pins
P1SEL1 &= ~(BIT4 | BIT5); // set 2-UART pin as second function
P1SEL0 |= (BIT4 | BIT5); // set 2-UART pin as second function
if(Lora_Param.baud == 7)
UA0_Init(115200);
else if(Lora_Param.baud == 5)
UA0_Init(38400);
else
UA0_Init(9600);
#if 0 // <20><><EFBFBD>ô<EFBFBD>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
// Configure UART pins
P2SEL1 &= ~(BIT5 | BIT6); // set 2-UART pin as second function
P2SEL0 |= (BIT5 | BIT6); // set 2-UART pin as second function
// Configure UART
UCA1CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+
// Baud Rate calculation
UCA1BR0 = 4; // 8000000/16/115200//<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>16 UCOS16λҪ<CEBB><D2AA>λ
UCA1BR1 = 0; // Fractional portion = 0.44444
UCA1MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢<><CEA2>Baud Rate
UCA1CTLW0 &= ~UCSWRST; // Initialize eUSCI
UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt
// <20><>ӡ<EFBFBD><D3A1>λԭ<CEBB><D4AD>(<28><>Դ<EFBFBD><D4B4><EFBFBD>𣬲<EFBFBD><F0A3ACB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ź<EFBFBD>)
PRINTF("\nModule reseted: %04X\n", PMMIFG);
#else // <20><><EFBFBD><EFBFBD>MD0<44><30>MD1ģʽ
P2SEL1 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO
P2SEL0 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO
P2DIR &= ~(BIT5 | BIT6); // Input
P2REN |= (BIT5 | BIT6); // enable pull
P2OUT &= ~(BIT5 | BIT6); // pull-down
P2DIR |= BIT3; // Output
P2OUT |= BIT3; // Output high
#endif
_EINT();
#if 0
// <20><>ӡ<EFBFBD><D3A1>λԭ<CEBB><D4AD>(<28><>Դ<EFBFBD><D4B4><EFBFBD>𣬲<EFBFBD><F0A3ACB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ź<EFBFBD>)
RF_RxBuf[0] = PMMIFG >> 8;
RF_RxBuf[1] = PMMIFG & 0xFF;
RF_RxBuf_Length = 2;
RF_RxBuf_offset = 0;
UCA0IE |= UCTXIE;
while(UCA0IE & UCTXIE);
#endif
// <20><><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λԭ<CEBB><D4AD>
SYSRSTIV;
//<2F><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>
uint8_t try_count = 3; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>3<EFBFBD><33>
while(try_count)
{
if(SX127x_initLora(&Lora_Param) == NORMAL)
break;
try_count--;
}
if(try_count == 0) //<2F><><EFBFBD>߳<EFBFBD>ʼ<EFBFBD><CABC>ʧ<EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
{
//P3OUT ^= 0xC0;
LPM4;
}
// <20><>ʼ<EFBFBD><CABC><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>ģʽ
LSD_RF_RXmode(RF_PAYLOAD_LEN);
// Ĭ<>Ϸ<EFBFBD><CFB7><EFBFBD><EFBFBD>ŵ<EFBFBD>
sendCh = Lora_Param.ch;
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ź<EFBFBD>: <20><>ʱʱ<CAB1><CAB1>Ϊ2^27/SMCLK<4C><4B><EFBFBD><EFBFBD>8000000<30><30>Ƶ<EFBFBD><C6B5>ԼΪ16s
WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1);
while(1)
{
#if 1
// TODO: ι<><CEB9>
WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1);
// <20><><EFBFBD><EFBFBD>ģʽ
if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6))
{
if(UA0_RxBuf_Length - UA0_RxBuf_offset >= sizeof(Lora_Param))
{
if(UA0_RxBuf[UA0_RxBuf_offset] == 0xC2)
{
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
memmove(&Lora_Param, UA0_RxBuf + UA0_RxBuf_offset, sizeof(Lora_Param));
// <20>ߵ<EFBFBD><DFB5><EFBFBD>ַ<EFBFBD>ߵ<EFBFBD><DFB5>ֽ<EFBFBD>
Lora_Param.addr = (Lora_Param.addr << 8) | (Lora_Param.addr >> 8);
//<2F><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>
uint8_t try_count = 3; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>3<EFBFBD><33>
while(try_count)
{
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>б仯<D0B1><E4BBAF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>
if(SX127x_initLora(&Lora_Param) == NORMAL)
break;
try_count--;
}
if(try_count == 0) //<2F><><EFBFBD>߳<EFBFBD>ʼ<EFBFBD><CABC>ʧ<EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
{
//P3OUT ^= 0xC0;
LPM4;
}
// Ĭ<>ϴ<EFBFBD><CFB4>ڽ<EFBFBD><DABD><EFBFBD>ģʽ
LSD_RF_RXmode(RF_PAYLOAD_LEN);
// Ĭ<>Ϸ<EFBFBD><CFB7><EFBFBD><EFBFBD>ŵ<EFBFBD>
sendCh = Lora_Param.ch;
// Ӧ<><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
UA0_Response("OK\r\n");
// <20>ı䴮<C4B1>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>
if(Lora_Param.baud == 7)
UA0_Init(115200);
else if(Lora_Param.baud == 5)
UA0_Init(38400);
else
UA0_Init(9600);
}
UA0_RxBuf_offset = UA0_RxBuf_Length;
}
}
// ͸<><CDB8>ģʽ
else if((P2IN & (BIT5 | BIT6)) == 0)
#endif
{
if(UA0_RxBuf_Length > UA0_RxBuf_offset)
{
// <20><><EFBFBD>㴫<EFBFBD>䣬ָ<E4A3AC><D6B8>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>
if(Lora_Param.unicast) // <20><><EFBFBD>㷢<EFBFBD><E3B7A2>
{
if(UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 3)
sendCh = UA0_RxBuf[2];
}
else if(Lora_Param.freqcast) // ָ<><D6B8><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>
{
if(UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 1)
{
sendCh = UA0_RxBuf[0];
UA0_RxBuf_offset = 1; // <20><><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>
}
}
if(UA0_RxBuf_Length - UA0_RxBuf_offset >= RF_PAYLOAD_LEN)
{
LSD_RF_FreqSet(sendCh);
LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, RF_PAYLOAD_LEN);
UA0_RxBuf_offset += RF_PAYLOAD_LEN;
PRINTF("Send packet\n");
// <20>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
LSD_RF_FreqSet(Lora_Param.ch);
LSD_RF_RXmode(RF_PAYLOAD_LEN);
}
else if(UA0_Rx_Timeout)
{
LSD_RF_FreqSet(sendCh);
LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, UA0_RxBuf_Length - UA0_RxBuf_offset);
UA0_RxBuf_offset = UA0_RxBuf_Length;
PRINTF("Send packet\n");
// <20>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
LSD_RF_FreqSet(Lora_Param.ch);
LSD_RF_RXmode(RF_PAYLOAD_LEN);
}
}
}
if(UA0_Rx_Timeout && UA0_RxBuf_offset == UA0_RxBuf_Length)
P2OUT |= BIT3; // Output high
}
}
// Port 1 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(PORT1_VECTOR))) Port_1 (void)
#else
#error Compiler not supported!
#endif
{
uint8_t offset = 0;
uint8_t len[1] = {0};
uint8_t buf[RF_PAYLOAD_LEN];
if(DIO0_IFG&DIO0_BIT) //<2F><><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD><EFBFBD>жϴ<D0B6><CFB4><EFBFBD>
{
// <20><><EFBFBD>ж<EFBFBD>
DIO0_IFG &= ~DIO0_BIT;
// <20><>ȡRF<52><46><EFBFBD><EFBFBD>
LSD_RF_RxVariPacket(buf, len); //<2F><><EFBFBD>տɱ<D5BF><C9B1><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD>ʣ<EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD>ý<EFBFBD><C3BD>չ̶<D5B9><CCB6><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>
if(len[0] == 0)
return;
TA1CTL = MC__STOP | TACLR; // ֹͣ<CDA3><D6B9>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
TA1CTL = TASSEL__ACLK | MC__UP; // <20><><EFBFBD>¿<EFBFBD>ʼ<EFBFBD><CABC>ʱ
offset = 0;
if(RF_Rx_Timeout) // <20>µ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD>
{
RF_Rx_Timeout = 0;
// <20><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
RF_RxBuf_Length = 0;
RF_RxBuf_offset = 0;
if(Lora_Param.unicast)
{
// <20><><EFBFBD>㴫<EFBFBD>䣬<EFBFBD><E4A3AC>ַ<EFBFBD><D6B7><EFBFBD>ŵ<EFBFBD>У<EFBFBD><D0A3>ʧ<EFBFBD><CAA7>
if(len[0] <= 3 || buf[2] != Lora_Param.ch || ((buf[0] << 8) | buf[1]) != Lora_Param.addr)
return;
// ǰ3<C7B0><33><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>
offset = 3;
len[0] -= offset;
}
}
PRINTF("Recv packet\n");
// ͸<><CDB8>ģʽ
if((P2IN & (BIT5 | BIT6)) == 0)
{
if(RF_RxBuf_Length + len[0] <= TRAN_BUF_SIZE)
{
memmove(RF_RxBuf + RF_RxBuf_Length, buf + offset, len[0]);
// <20>жϷ<D0B6>ʽ<EFBFBD>򴮿<EFBFBD>ת<EFBFBD><D7AA>
RF_RxBuf_Length += len[0];
UCA0IE |= UCTXIE;
}
}
}
}
// Timer0 A0 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = TIMER0_A0_VECTOR
__interrupt void Timer0_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) Timer0_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
// ֹͣ<CDA3><D6B9>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
TA0CTL = MC__STOP | TACLR;
// <20><><EFBFBD>ڽ<EFBFBD><DABD>ճ<EFBFBD>ʱ
UA0_Rx_Timeout = 1;
}
// Timer1 A0 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = TIMER1_A0_VECTOR
__interrupt void Timer1_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER1_A0_VECTOR))) Timer1_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
// ֹͣ<CDA3><D6B9>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
TA1CTL = MC__STOP | TACLR;
// RF<52><46><EFBFBD>ճ<EFBFBD>ʱ
RF_Rx_Timeout = 1;
}
// UAR0 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
// <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
if((UCA0IE & UCRXIE) && (UCA0IFG & UCRXIFG))
{
uint8_t c = UCA0RXBUF;
TA0CTL = MC__STOP | TACLR; // ֹͣ<CDA3><D6B9>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
TA0CTL = TASSEL__ACLK | MC__UP; // <20><><EFBFBD>¿<EFBFBD>ʼ<EFBFBD><CABC>ʱ
if(UA0_Rx_Timeout) // <20>µ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD>
{
UA0_Rx_Timeout = 0;
// <20><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
UA0_RxBuf_Length = 0;
UA0_RxBuf_offset = 0;
}
if(UA0_RxBuf_Length < TRAN_BUF_SIZE)
{
#if 1
// <20><><EFBFBD><EFBFBD>ģʽ
if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6))
{
// <20><>1<EFBFBD><31><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>Ϊ0xC2
if(UA0_RxBuf_Length > 0 || c == 0xC2)
UA0_RxBuf[UA0_RxBuf_Length++] = c;
}
// ͸<><CDB8>ģʽ
else if((P2IN & (BIT5 | BIT6)) == 0)
#endif
{
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>
UA0_RxBuf[UA0_RxBuf_Length++] = c;
}
P2OUT &= ~BIT3; // Output low
}
}
// <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
if((UCA0IE & UCTXIE) && (UCA0IFG & UCTXIFG))
{
UCA0TXBUF = RF_RxBuf[RF_RxBuf_offset++]; // <20><><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD>
if(RF_RxBuf_offset >= RF_RxBuf_Length) // ȫ<><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
{
// <20><>ֹ<EFBFBD>ж<EFBFBD>
UCA0IE &= ~UCTXIE;
}
}
}