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ShipCentralControl/RF-AP/20201015鼎力调通/FR2433-RFSX.h

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增加RF-AP程序
2025-04-07 09:18:02 +08:00
#ifndef FR2433_RFSX
#define FR2433_RFSX
////////////////////////////////////////////////////////////////////////////////
// <20><>Ȩ: Haybin.Wu@studio
// <20>ļ<EFBFBD><C4BC><EFBFBD>:
// <20>汾<EFBFBD><E6B1BE> V1.0
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: IAR v6.20
// <20><><EFBFBD><EFBFBD>: Haybin
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 2016.05
// <20><><EFBFBD><EFBFBD>: API for FR4133
// <20>޸<EFBFBD><DEB8><EFBFBD>־<EFBFBD><D6BE>
////////////////////////////////////////////////////////////////////////////////
#include <MSP430FR2433.h>
#include <stdbool.h>
//======================================================================================
#define CPU_MCLK 8000000
#define DelayUs(us) __delay_cycles((CPU_MCLK/1000000UL) * us)
#define DelayMs(ms) __delay_cycles((CPU_MCLK/1000UL) * ms)
////////////////////////////////////////////////////////////////////////////////
//ֻ<><D6BB><EFBFBD>޸<EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//SX1276 SPI I/O definitions
#define SPI_PSEL P1SEL0
#define SPI_PDIR P1DIR
#define SPI_POUT P1OUT
#define SPI_SI_BIT BIT2
#define SPI_SO_BIT BIT3
#define SPI_CLK_BIT BIT1
#define SPI_NSS_BIT BIT0
#define SPI_NSS_PDIR P1DIR
#define SPI_NSS_POUT P1OUT
//DIO0
#define DIO0_BIT BIT6
#define DIO0_DIR P1DIR
#define DIO0_IFG P1IFG
#define DIO0_IES P1IES
#define DIO0_IE P1IE
//DIO1
#define DIO1_BIT BIT7
#define DIO1_DIR P1DIR
#define DIO1_IFG P1IFG
#define DIO1_IES P1IES
#define DIO1_IE P1IE
//DIO3
#define DIO3_BIT BIT4
#define DIO3_DIR P2DIR
#define DIO3_IFG P2IFG
#define DIO3_IES P2IES
#define DIO3_IE P2IE
//RST
#define RST_BIT BIT1
#define RST_PDIR P3DIR
#define RST_POUT P3OUT
////////////////////////////////////////////////////////////////////////////////
//SX1276 SPI I/O definitions
//NSS
#define SPI_NSS_DIR_OUT SPI_NSS_PDIR |= SPI_NSS_BIT //Ƭѡ out
#define SPI_NSS_OUT_1 SPI_NSS_POUT |= SPI_NSS_BIT //1
#define SPI_NSS_OUT_0 SPI_NSS_POUT &= (~SPI_NSS_BIT) //1
//DIO0
#define DIO0_IFG_H DIO0_IFG |= DIO0_BIT
#define DIO0_IFG_L DIO0_IFG &= ~DIO0_BIT
#define DIO0_IES_H DIO0_IES |= DIO0_BIT
#define DIO0_IES_L DIO0_IES &= ~DIO0_BIT
#define DIO0_IE_H DIO0_IE |= DIO0_BIT
#define DIO0_IE_L DIO0_IE &= ~DIO0_BIT
//DIO1
#define DIO1_IFG_H DIO1_IFG |= DIO1_BIT
#define DIO1_IFG_L DIO1_IFG &= ~DIO1_BIT
#define DIO1_IES_H DIO1_IES |= DIO1_BIT
#define DIO1_IES_L DIO1_IES &= ~DIO1_BIT
#define DIO1_IE_H DIO1_IE |= DIO0_BIT
#define DIO1_IE_L DIO1_IE &= ~DIO1_BIT
//DIO3
#define DIO3_IFG_H DIO3_IFG |= DIO3_BIT
#define DIO3_IFG_L DIO3_IFG &= ~DIO3_BIT
#define DIO3_IES_H DIO3_IES |= DIO3_BIT
#define DIO3_IES_L DIO3_IES &= ~DIO3_BIT
#define DIO3_IE_H DIO3_IE |= DIO3_BIT
#define DIO3_IE_L DIO3_IE &= ~DIO3_BIT
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : SX1276 I/O pins definitions
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void SX1276Init_IO( void )
{
//DIO0ΪP2.0
//P2DIR &= ~BIT0;
//P2OUT |= BIT0; // Configure DIO0 as pulled-up
//P2REN |= BIT0; // DIO0pull-up register enable
DIO0_DIR&=~DIO0_BIT;
DIO0_IES_L; // DIO0 Hi/Low edge
DIO0_IE_L; // DIO0 interrupt enabled
DIO0_IFG_L; // DIO0IFG cleared
//DIO1ΪP2.1
//P2DIR &= ~BIT1;
//P2OUT |= BIT1; // Configure DIO1 as pulled-up
//P2REN |= BIT1; // DIO1pull-up register enable
DIO1_DIR&=~DIO1_BIT;
DIO1_IES_L; // DIO1 Hi/Low edge
DIO1_IE_L; // DIO1 interrupt enabled
DIO1_IFG_L; // DIO1IFG cleared
//DIO3ΪP2.3
//P2DIR &= ~BIT3;
//P2OUT |= BIT3; // Configure DIO3 as pulled-up
//P2REN |= BIT3; // DIO3pull-up register enable
DIO3_DIR&=~DIO3_BIT;
DIO3_IES_L; // DIO3 Hi/Low edge
DIO3_IE_L; // DIO3 interrupt enabled
DIO3_IFG_L; // DIO3IFG cleared
//SX1276 SPI I/O definitions
// Configure SPI
//SPI SET
SPI_NSS_DIR_OUT;
SPI_NSS_OUT_1; // /CS disable
// SPI option select
SPI_PSEL |= SPI_SI_BIT+SPI_SO_BIT+SPI_CLK_BIT;
UCB0CTLW0 |= UCSWRST; // **Put state machine in reset**
UCB0CTLW0 |= UCMST|UCSYNC|UCCKPH|UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCB0CTLW0 |= UCSSEL__SMCLK; // SMCLK
UCB0BR0 = 1; // /2,fBitClock = fBRCLK/(UCBRx+1).
UCB0BR1 = 0; //
UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
//SX1276 RESET I/O definitions
RST_PDIR |= RST_BIT;
RST_POUT |= RST_BIT;
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><><EFBFBD><EFBFBD>˯<EFBFBD>߳<EFBFBD>ʱ<EFBFBD><CAB1>ʱ<EFBFBD><CAB1>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void ON_Sleep_Timerout(void)
{
//Timer1_A3 setup
TA1R =0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
TA1CCTL0 = CCIE; // TACCR0 interrupt enabled
TA1CCR0 = 32768;
TA0CTL |= TASSEL_1 | MC_1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ʱ<EFBFBD><CAB1>
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20>ر<EFBFBD>˯<EFBFBD>߳<EFBFBD>ʱ<EFBFBD><CAB1>ʱ<EFBFBD><CAB1>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void OFF_Sleep_Timerout(void)
{
//TA0R =0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
TA1CCTL0 = CCIE; // TACCR0 interrupt enabled
TA1CCR0 = 32768;
TA0CTL = TASSEL_1 | MC_0; //<2F>رն<D8B1>ʱ<EFBFBD><CAB1>
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF <20><>λ
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void SX1276Reset(void)
{
RST_POUT &= ~RST_BIT; //Ӳ<><D3B2><EFBFBD><EFBFBD>λIO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0
DelayMs(6); //<2F><>ʱ
RST_POUT |= RST_BIT; //<2F><><EFBFBD><EFBFBD>Ϊ1
DelayMs(5);
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF <20><><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t addr,<2C>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ uint8_t *buffer,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8> uint8_t sizeָ<65>볤<EFBFBD><EBB3A4>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void SX1276WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size )
{
uint8_t i;
SPI_PSEL |= SPI_SO_BIT;//SPI<50><49>bug<75><67><EFBFBD><EFBFBD><EFBFBD>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD>쳣
SPI_NSS_OUT_0;
// _NOP();_NOP();_NOP();_NOP();
// _NOP();_NOP();_NOP();_NOP();
UCB0IFG &= ~UCRXIFG; // Clear flag
UCB0TXBUF = (addr | 0x80); // Send address
while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish
UCB0IFG &= ~UCTXIFG; // Clear flag
for( i = 0; i < size; i++ )
{
UCB0TXBUF = buffer[i]; // Send data
while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish
UCB0IFG &= ~UCTXIFG;
}
// _NOP();_NOP();_NOP();_NOP();
// _NOP();_NOP();_NOP();_NOP();
SPI_NSS_OUT_1;
SPI_PSEL &= ~SPI_SO_BIT;//SPI<50><49>bug<75><67><EFBFBD><EFBFBD><EFBFBD>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD>쳣
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF <20><><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t addr,<2C>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ uint8_t *buffer,<2C>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8> uint8_t sizeҪ<65><D2AA><EFBFBD>ij<EFBFBD><C4B3><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><><EFBFBD>ݷ<EFBFBD><DDB7>ص<EFBFBD>*buffer<65><72>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void SX1276ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size )
{
uint8_t i;
SPI_PSEL |= SPI_SO_BIT;//SPI<50><49>bug<75><67><EFBFBD><EFBFBD><EFBFBD>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD>쳣
SPI_NSS_OUT_0;
// _NOP();_NOP();_NOP();_NOP();
// _NOP();_NOP();_NOP();_NOP();
UCB0IFG &= ~UCRXIFG; // Clear flag
UCB0TXBUF = (addr & 0x7F); // Send address
while (!(UCB0IFG&UCTXIFG)); // Wait for end of addr byte TX
UCB0IFG &= ~UCTXIFG; // Clear flag
for( i = 0; i < size; i++ )
{
UCB0TXBUF = 0; //Initiate next data RX
while (!(UCB0IFG&UCRXIFG)); // Wait for RX to finish
buffer[i] = UCB0RXBUF; // Store data from last data RX
//<2F><>ȡUCB0RXBUF<55><46><EFBFBD><EFBFBD>IFG<46>Զ<EFBFBD>Reset
}
// _NOP();_NOP();_NOP();_NOP();
// _NOP();_NOP();_NOP();_NOP();
SPI_NSS_OUT_1;
SPI_PSEL &= ~SPI_SO_BIT;//SPI<50><49>bug<75><67><EFBFBD><EFBFBD><EFBFBD>Ĺ<EFBFBD><C4B9><EFBFBD><EFBFBD>쳣
UCB0IFG=0;
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF <20><><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַд1<D0B4>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t addr,<2C>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ uint8_t data<74><61><EFBFBD><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> :
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void SX1276Write( uint8_t addr, uint8_t data )
{
SX1276WriteBuffer( addr, &data, 1 );
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF <20><><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>1<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t addr,<2C>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ uint8_t *data<74><61><EFBFBD><EFBFBD><EFBFBD>ݴ洢<DDB4><E6B4A2>ַ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> :
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void SX1276Read( uint8_t addr, uint8_t *data )
{
SX1276ReadBuffer( addr, data, 1 );
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF <20><>FIFOд<4F><D0B4><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t *buffer,<2C><><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8> uint8_t size<7A><65><EFBFBD><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> :
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void SX1276WriteFifo( uint8_t *buffer, uint8_t size )
{
SX1276WriteBuffer( 0, buffer, size );
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF <20><>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t *buffer,<2C><><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8> uint8_t size<7A><65><EFBFBD><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : uint8_t *buffer <20>洢<EFBFBD><E6B4A2>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void SX1276ReadFifo( uint8_t *buffer, uint8_t size )
{
SX1276ReadBuffer( 0, buffer, size );
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF TX/RX<52><58>PA<50>л<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : bool txEnable <20>л<EFBFBD><D0BB>߼<EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :<3A>棺<EFBFBD><E6A3BA>ΪTX<54><58><EFBFBD>٣<EFBFBD><D9A3><EFBFBD>ΪRX ΪӲ<CEAA><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PA<50><41><EFBFBD><EFBFBD>IO<49><4F>
////////////////////////////////////////////////////////////////////////////////
void SX1276WriteRxTx( bool txEnable )
{
if( txEnable != 0 ) //<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD>棬ΪTX
{
;
}
else //Ϊ<>٣<EFBFBD>ΪRX
{
;
}
}
//*****************************************************************************************
#endif