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ShipCentralControl/RF-AP/20201020内部调通/RF_SX1276.h

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增加RF-AP程序
2025-04-07 09:18:02 +08:00
////////////////////////////////////////////////////////////////////////////////
// <20><>Ȩ: Haybin.Wu@studio
// <20>ļ<EFBFBD><C4BC><EFBFBD>:
// <20>汾<EFBFBD><E6B1BE> V1.0
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: IAR v6.20
// <20><><EFBFBD><EFBFBD>: Haybin
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 2016.05
// <20><><EFBFBD><EFBFBD>: API
// <20>޸<EFBFBD><DEB8><EFBFBD>־<EFBFBD><D6BE>
////////////////////////////////////////////////////////////////////////////////
// Modify by Qian Xianghong
// 2020.10
// <20>޸<EFBFBD><DEB8><EFBFBD>־<EFBFBD><D6BE>
// 1. LSD_RF_SendPacket()<29><><EFBFBD><EFBFBD>:
// <20>޸<EFBFBD><DEB8>ж<EFBFBD>DIO0<4F><30>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
// ǰ<><C7B0><EFBFBD>볤<EFBFBD><EBB3A4><EFBFBD>޸<EFBFBD>Ϊ8.<2E><>Ĭ<EFBFBD><C4AC>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD>м<EFBFBD><D0BC><EFBFBD>һ<EFBFBD>£<EFBFBD>
// 2. LSD_RF_RXmode()<29><><EFBFBD><EFBFBD>:
// <20><><EFBFBD><EFBFBD>PayloadCrcError<6F><72>ʶ<EFBFBD><CAB6>
// ǰ<><C7B0><EFBFBD>볤<EFBFBD><EBB3A4><EFBFBD>޸<EFBFBD>Ϊ8.<2E><>Ĭ<EFBFBD><C4AC>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD>м<EFBFBD><D0BC><EFBFBD>һ<EFBFBD>£<EFBFBD>
// 3. LSD_RF_RxVariPacket()<29><><EFBFBD><EFBFBD>:
// <20>ж<EFBFBD>RxDone<6E><65>PayloadCRCError<6F><72>ʶ<EFBFBD><CAB6>
// <20>ȶ<EFBFBD>ȡREG_LR_FIFORXCURRENTADDR<44>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>ٴӸõ<D3B8>ַ<EFBFBD><D6B7>ʼ<EFBFBD><CABC>ȡ<EFBFBD><C8A1><EFBFBD>ݡ<EFBFBD>
// 4. LSD_RF_RxFixiPacket()<29><><EFBFBD><EFBFBD>:
// <20>ж<EFBFBD>RxDone<6E><65>PayloadCRCError<6F><72>ʶ<EFBFBD><CAB6>
// 5. <20><><EFBFBD><EFBFBD>SX127x_initLora()<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڸ<EFBFBD><DAB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>س<EFBFBD>ʼ<EFBFBD><CABC>LoRa<52><61><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
////////////////////////////////////////////////////////////////////////////////
#include <stdbool.h>
#include <stdint.h>
#include "FR2433-RFSX.h"
#ifndef RF_SX1276
#define RF_SX1276
uint8_t LSD_RF_FreqSet(uint8_t ch);
uint8_t LSD_RF_PoutSet(uint8_t power);
//===================================<3D><><EFBFBD><EFBFBD>===================================================
#define RF_PAYLOAD_LEN (64)
#pragma pack(push, 1)
// LORA<52><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҫ<EFBFBD><D2AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
typedef struct
{
uint8_t sof; // ǰ<><C7B0><EFBFBD>룬<EFBFBD>̶<EFBFBD>Ϊ0xC2
uint16_t addr; // ͨ<>ŵ<EFBFBD>ַ
unsigned char sf : 3; // <20><>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>: 0-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1-7,...,6-12,7-<2D><><EFBFBD><EFBFBD>
unsigned char baud : 3; // <20><><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD>ʣ<EFBFBD>3-9600,7-115200, <20><><EFBFBD>ౣ<EFBFBD><E0B1A3>
unsigned char cr : 2; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 0-4/5,1-4/6,2-4/7,3-4/8
uint8_t ch; // ͨ<><CDA8><EFBFBD>ŵ<EFBFBD>: 0~40(470M~510M),<2C><><EFBFBD>ౣ<EFBFBD><E0B1A3>
unsigned char power : 2; // Power: 0-20dBm,1-17dBm,2-14dBm,3-11dBm
unsigned char freqcast: 1; // <20>Ƿ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>
unsigned char bw : 4; // 0-7.8kHz,1-10.4kHz,...,9-500kHz, <20><><EFBFBD>ౣ<EFBFBD><E0B1A3>
unsigned char unicast : 1; // <20>Ƿ񶨵㷢<F1B6A8B5><E3B7A2>
} lora_param_t;
#pragma pack(pop)
//===================================<3D><><EFBFBD><EFBFBD>===================================================
/*!
* SX1276 LoRa General parameters definition
*/
typedef struct sLoRaSettings
{
uint32_t RFFrequency;
int8_t Power;
uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz,
// 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved]
uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips]
uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
bool CrcOn; // [0: OFF, 1: ON]
bool ImplicitHeaderOn; // [0: OFF, 1: ON]
bool RxSingleOn; // [0: Continuous, 1 Single]
bool FreqHopOn; // [0: OFF, 1: ON]
uint8_t HopPeriod; // Hops every frequency hopping period symbols
uint32_t TxPacketTimeout;
uint32_t RxPacketTimeout;
uint8_t PayloadLength;
}tLoRaSettings;
/*!
* RF packet definition
*/
#define RF_BUFFER_SIZE_MAX 128
#define RF_BUFFER_SIZE 80
/*!
* RF state machine
*/
//LoRa
typedef enum
{
RFLR_STATE_IDLE,
RFLR_STATE_RX_INIT,
RFLR_STATE_RX_RUNNING,
RFLR_STATE_RX_DONE,
RFLR_STATE_RX_TIMEOUT,
RFLR_STATE_TX_INIT,
RFLR_STATE_TX_RUNNING,
RFLR_STATE_TX_DONE,
RFLR_STATE_TX_TIMEOUT,
RFLR_STATE_CAD_INIT,
RFLR_STATE_CAD_RUNNING,
}tRFLRStates;
/*!
* SX1276 definitions
*/
#define XTAL_FREQ 32000000
#define FREQ_STEP 61.03515625
/*!
* SX1276 Internal registers Address
*/
#define REG_LR_FIFO 0x00
// Common settings
#define REG_LR_OPMODE 0x01
//#define REG_LR_BANDSETTING 0x04
#define REG_LR_FRFMSB 0x06
#define REG_LR_FRFMID 0x07
#define REG_LR_FRFLSB 0x08
// Tx settings
#define REG_LR_PACONFIG 0x09
#define REG_LR_PARAMP 0x0A
#define REG_LR_OCP 0x0B
// Rx settings
#define REG_LR_LNA 0x0C
// LoRa registers
#define REG_LR_FIFOADDRPTR 0x0D
#define REG_LR_FIFOTXBASEADDR 0x0E
#define REG_LR_FIFORXBASEADDR 0x0F
#define REG_LR_FIFORXCURRENTADDR 0x10
#define REG_LR_IRQFLAGSMASK 0x11
#define REG_LR_IRQFLAGS 0x12
#define REG_LR_NBRXBYTES 0x13
#define REG_LR_RXHEADERCNTVALUEMSB 0x14
#define REG_LR_RXHEADERCNTVALUELSB 0x15
#define REG_LR_RXPACKETCNTVALUEMSB 0x16
#define REG_LR_RXPACKETCNTVALUELSB 0x17
#define REG_LR_MODEMSTAT 0x18
#define REG_LR_PKTSNRVALUE 0x19
#define REG_LR_PKTRSSIVALUE 0x1A
#define REG_LR_RSSIVALUE 0x1B
#define REG_LR_HOPCHANNEL 0x1C
#define REG_LR_MODEMCONFIG1 0x1D
#define REG_LR_MODEMCONFIG2 0x1E
#define REG_LR_SYMBTIMEOUTLSB 0x1F
#define REG_LR_PREAMBLEMSB 0x20
#define REG_LR_PREAMBLELSB 0x21
#define REG_LR_PAYLOADLENGTH 0x22
#define REG_LR_PAYLOADMAXLENGTH 0x23
#define REG_LR_HOPPERIOD 0x24
#define REG_LR_FIFORXBYTEADDR 0x25
#define REG_LR_MODEMCONFIG3 0x26
// end of documented register in datasheet
// I/O settings
#define REG_LR_DIOMAPPING1 0x40
#define REG_LR_DIOMAPPING2 0x41
// Version
#define REG_LR_VERSION 0x42
// Additional settings
#define REG_LR_PLLHOP 0x44
#define REG_LR_TCXO 0x4B
#define REG_LR_PADAC 0x4D
#define REG_LR_FORMERTEMP 0x5B
#define REG_LR_BITRATEFRAC 0x5D
#define REG_LR_AGCREF 0x61
#define REG_LR_AGCTHRESH1 0x62
#define REG_LR_AGCTHRESH2 0x63
#define REG_LR_AGCTHRESH3 0x64
/*!
* SX1276 LoRa bit control definition
*/
/*!
* RegFifo
*/
/*!
* RegOpMode
*/
#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7
#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default
#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00
#define RFLR_OPMODE_MASK 0xF8
#define RFLR_OPMODE_SLEEP 0x00
#define RFLR_OPMODE_STANDBY 0x01 // Default
#define RFLR_OPMODE_SYNTHESIZER_TX 0x02
#define RFLR_OPMODE_TRANSMITTER 0x03
#define RFLR_OPMODE_SYNTHESIZER_RX 0x04
#define RFLR_OPMODE_RECEIVER 0x05
// LoRa specific modes
#define RFLR_OPMODE_RECEIVER_SINGLE 0x06
#define RFLR_OPMODE_CAD 0x07
/*!
* RegBandSetting
*/
#define RFLR_BANDSETTING_MASK 0x3F
#define RFLR_BANDSETTING_AUTO 0x00 // Default
#define RFLR_BANDSETTING_DIV_BY_1 0x40
#define RFLR_BANDSETTING_DIV_BY_2 0x80
#define RFLR_BANDSETTING_DIV_BY_6 0xC0
/*!
* RegPaConfig
*/
#define RFLR_PACONFIG_PASELECT_MASK 0x7F
#define RFLR_PACONFIG_PASELECT_PABOOST 0x80
#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F
#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
/*!
* RegPaRamp
*/
#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF
#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10
#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default
#define RFLR_PARAMP_MASK 0xF0
#define RFLR_PARAMP_3400_US 0x00
#define RFLR_PARAMP_2000_US 0x01
#define RFLR_PARAMP_1000_US 0x02
#define RFLR_PARAMP_0500_US 0x03
#define RFLR_PARAMP_0250_US 0x04
#define RFLR_PARAMP_0125_US 0x05
#define RFLR_PARAMP_0100_US 0x06
#define RFLR_PARAMP_0062_US 0x07
#define RFLR_PARAMP_0050_US 0x08
#define RFLR_PARAMP_0040_US 0x09 // Default
#define RFLR_PARAMP_0031_US 0x0A
#define RFLR_PARAMP_0025_US 0x0B
#define RFLR_PARAMP_0020_US 0x0C
#define RFLR_PARAMP_0015_US 0x0D
#define RFLR_PARAMP_0012_US 0x0E
#define RFLR_PARAMP_0010_US 0x0F
/*!
* RegOcp
*/
#define RFLR_OCP_MASK 0xDF
#define RFLR_OCP_ON 0x20 // Default
#define RFLR_OCP_OFF 0x00
#define RFLR_OCP_TRIM_MASK 0xE0
#define RFLR_OCP_TRIM_045_MA 0x00
#define RFLR_OCP_TRIM_050_MA 0x01
#define RFLR_OCP_TRIM_055_MA 0x02
#define RFLR_OCP_TRIM_060_MA 0x03
#define RFLR_OCP_TRIM_065_MA 0x04
#define RFLR_OCP_TRIM_070_MA 0x05
#define RFLR_OCP_TRIM_075_MA 0x06
#define RFLR_OCP_TRIM_080_MA 0x07
#define RFLR_OCP_TRIM_085_MA 0x08
#define RFLR_OCP_TRIM_090_MA 0x09
#define RFLR_OCP_TRIM_095_MA 0x0A
#define RFLR_OCP_TRIM_100_MA 0x0B // Default
#define RFLR_OCP_TRIM_105_MA 0x0C
#define RFLR_OCP_TRIM_110_MA 0x0D
#define RFLR_OCP_TRIM_115_MA 0x0E
#define RFLR_OCP_TRIM_120_MA 0x0F
#define RFLR_OCP_TRIM_130_MA 0x10
#define RFLR_OCP_TRIM_140_MA 0x11
#define RFLR_OCP_TRIM_150_MA 0x12
#define RFLR_OCP_TRIM_160_MA 0x13
#define RFLR_OCP_TRIM_170_MA 0x14
#define RFLR_OCP_TRIM_180_MA 0x15
#define RFLR_OCP_TRIM_190_MA 0x16
#define RFLR_OCP_TRIM_200_MA 0x17
#define RFLR_OCP_TRIM_210_MA 0x18
#define RFLR_OCP_TRIM_220_MA 0x19
#define RFLR_OCP_TRIM_230_MA 0x1A
#define RFLR_OCP_TRIM_240_MA 0x1B
/*!
* RegLna
*/
#define RFLR_LNA_GAIN_MASK 0x1F
#define RFLR_LNA_GAIN_G1 0x20 // Default
#define RFLR_LNA_GAIN_G2 0x40
#define RFLR_LNA_GAIN_G3 0x60
#define RFLR_LNA_GAIN_G4 0x80
#define RFLR_LNA_GAIN_G5 0xA0
#define RFLR_LNA_GAIN_G6 0xC0
#define RFLR_LNA_BOOST_LF_MASK 0xE7
#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default
#define RFLR_LNA_BOOST_LF_GAIN 0x08
#define RFLR_LNA_BOOST_LF_IP3 0x10
#define RFLR_LNA_BOOST_LF_BOOST 0x18
#define RFLR_LNA_RXBANDFORCE_MASK 0xFB
#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04
#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default
#define RFLR_LNA_BOOST_HF_MASK 0xFC
#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default
#define RFLR_LNA_BOOST_HF_ON 0x03
/*!
* RegFifoAddrPtr
*/
#define RFLR_FIFOADDRPTR 0x00 // Default
/*!
* RegFifoTxBaseAddr
*/
#define RFLR_FIFOTXBASEADDR 0x80 // Default
/*!
* RegFifoTxBaseAddr
*/
#define RFLR_FIFORXBASEADDR 0x00 // Default
/*!
* RegFifoRxCurrentAddr (Read Only)
*/
/*!
* RegIrqFlagsMask
*/
#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
#define RFLR_IRQFLAGS_RXDONE_MASK 0x40
#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
#define RFLR_IRQFLAGS_TXDONE_MASK 0x08
#define RFLR_IRQFLAGS_CADDONE_MASK 0x04
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
/*!
* RegIrqFlags
*/
#define RFLR_IRQFLAGS_RXTIMEOUT 0x80
#define RFLR_IRQFLAGS_RXDONE 0x40
#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
#define RFLR_IRQFLAGS_VALIDHEADER 0x10
#define RFLR_IRQFLAGS_TXDONE 0x08
#define RFLR_IRQFLAGS_CADDONE 0x04
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
#define RFLR_IRQFLAGS_CADDETECTED 0x01
/*!
* RegFifoRxNbBytes (Read Only) //
*/
/*!
* RegRxHeaderCntValueMsb (Read Only) //
*/
/*!
* RegRxHeaderCntValueLsb (Read Only) //
*/
/*!
* RegRxPacketCntValueMsb (Read Only) //
*/
/*!
* RegRxPacketCntValueLsb (Read Only) //
*/
/*!
* RegModemStat (Read Only) //
*/
#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
/*!
* RegPktSnrValue (Read Only) //
*/
/*!
* RegPktRssiValue (Read Only) //
*/
/*!
* RegRssiValue (Read Only) //
*/
/*!
* RegModemConfig1
*/
#define RFLR_MODEMCONFIG1_BW_MASK 0x0F
#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00
#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10
#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20
#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30
#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40
#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50
#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60
#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default
#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80
#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90
#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1
#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02
#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default
#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06
#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
/*!
* RegModemConfig2
*/
#define RFLR_MODEMCONFIG2_SF_MASK 0x0F
#define RFLR_MODEMCONFIG2_SF_6 0x60
#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
#define RFLR_MODEMCONFIG2_SF_8 0x80
#define RFLR_MODEMCONFIG2_SF_9 0x90
#define RFLR_MODEMCONFIG2_SF_10 0xA0
#define RFLR_MODEMCONFIG2_SF_11 0xB0
#define RFLR_MODEMCONFIG2_SF_12 0xC0
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
/*!
* RegHopChannel (Read Only)
*/
#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default
#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
/*!
* RegSymbTimeoutLsb
*/
#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
/*!
* RegPreambleLengthMsb
*/
#define RFLR_PREAMBLELENGTHMSB 0x00 // Default
/*!
* RegPreambleLengthLsb
*/
#define RFLR_PREAMBLELENGTHLSB 0x08 // Default
/*!
* RegPayloadLength
*/
#define RFLR_PAYLOADLENGTH 0x0E // Default
/*!
* RegPayloadMaxLength
*/
#define RFLR_PAYLOADMAXLENGTH 0xFF // Default
/*!
* RegHopPeriod
*/
#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
/*!
* RegDioMapping1
*/
#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO0_01 0x40
#define RFLR_DIOMAPPING1_DIO0_10 0x80
#define RFLR_DIOMAPPING1_DIO0_11 0xC0
#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO1_01 0x10
#define RFLR_DIOMAPPING1_DIO1_10 0x20
#define RFLR_DIOMAPPING1_DIO1_11 0x30
#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO2_01 0x04
#define RFLR_DIOMAPPING1_DIO2_10 0x08
#define RFLR_DIOMAPPING1_DIO2_11 0x0C
#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO3_01 0x01
#define RFLR_DIOMAPPING1_DIO3_10 0x02
#define RFLR_DIOMAPPING1_DIO3_11 0x03
/*!
* RegDioMapping2
*/
#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
#define RFLR_DIOMAPPING2_DIO4_01 0x40
#define RFLR_DIOMAPPING2_DIO4_10 0x80
#define RFLR_DIOMAPPING2_DIO4_11 0xC0
#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
#define RFLR_DIOMAPPING2_DIO5_01 0x10
#define RFLR_DIOMAPPING2_DIO5_10 0x20
#define RFLR_DIOMAPPING2_DIO5_11 0x30
#define RFLR_DIOMAPPING2_MAP_MASK 0xFE
#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
/*!
* RegVersion (Read Only)
*/
/*!
* RegAgcRef
*/
/*!
* RegAgcThresh1
*/
/*!
* RegAgcThresh2
*/
/*!
* RegAgcThresh3
*/
/*!
* RegFifoRxByteAddr (Read Only)
*/
/*!
* RegPllHop
*/
#define RFLR_PLLHOP_FASTHOP_MASK 0x7F
#define RFLR_PLLHOP_FASTHOP_ON 0x80
#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
/*!
* RegTcxo
*/
#define RFLR_TCXO_TCXOINPUT_MASK 0xEF
#define RFLR_TCXO_TCXOINPUT_ON 0x10
#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
/*!
* RegPaDac
*/
#define RFLR_PADAC_20DBM_MASK 0xF8
#define RFLR_PADAC_20DBM_ON 0x07
#define RFLR_PADAC_20DBM_OFF 0x04 // Default
/*!
* RegPll
*/
#define RFLR_PLL_BANDWIDTH_MASK 0x3F
#define RFLR_PLL_BANDWIDTH_75 0x00
#define RFLR_PLL_BANDWIDTH_150 0x40
#define RFLR_PLL_BANDWIDTH_225 0x80
#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
/*!
* RegPllLowPn
*/
#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
/*!
* RegModemConfig3
*/
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB
#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default
#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00
/*!
* RegFormerTemp
*/
typedef struct sSX1276LR
{
uint8_t RegFifo; // 0x00
// Common settings
uint8_t RegOpMode; // 0x01
uint8_t RegTestReserved02[0x06 - 0x02]; // 0x02-0x05
// uint8_t RegRes02; // 0x02
// uint8_t RegRes03; // 0x03
// uint8_t RegBandSetting; // 0x04
// uint8_t RegRes05; // 0x05
uint8_t RegFrfMsb; // 0x06
uint8_t RegFrfMid; // 0x07
uint8_t RegFrfLsb; // 0x08
// Tx settings
uint8_t RegPaConfig; // 0x09
uint8_t RegPaRamp; // 0x0A
uint8_t RegOcp; // 0x0B
// Rx settings
uint8_t RegLna; // 0x0C
// LoRa registers
uint8_t RegFifoAddrPtr; // 0x0D
uint8_t RegFifoTxBaseAddr; // 0x0E
uint8_t RegFifoRxBaseAddr; // 0x0F
uint8_t RegFifoRxCurrentAddr; // 0x10
uint8_t RegIrqFlagsMask; // 0x11
uint8_t RegIrqFlags; // 0x12
uint8_t RegNbRxBytes; // 0x13
uint8_t RegRxHeaderCntValueMsb; // 0x14
uint8_t RegRxHeaderCntValueLsb; // 0x15
uint8_t RegRxPacketCntValueMsb; // 0x16
uint8_t RegRxPacketCntValueLsb; // 0x17
uint8_t RegModemStat; // 0x18
uint8_t RegPktSnrValue; // 0x19
uint8_t RegPktRssiValue; // 0x1A
uint8_t RegRssiValue; // 0x1B
uint8_t RegHopChannel; // 0x1C
uint8_t RegModemConfig1; // 0x1D
uint8_t RegModemConfig2; // 0x1E
uint8_t RegSymbTimeoutLsb; // 0x1F
uint8_t RegPreambleMsb; // 0x20
uint8_t RegPreambleLsb; // 0x21
uint8_t RegPayloadLength; // 0x22
uint8_t RegMaxPayloadLength; // 0x23
uint8_t RegHopPeriod; // 0x24
uint8_t RegFifoRxByteAddr; // 0x25
uint8_t RegModemConfig3; // 0x26
uint8_t RegTestReserved27[0x31 - 0x27]; // 0x27-0x30
//void SX1276LoRaSetNbTrigPeaks( uint8_t value )<29>õ<EFBFBD>
uint8_t RegTestReserved31; // 0x31
uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x3F
// I/O settings
uint8_t RegDioMapping1; // 0x40
uint8_t RegDioMapping2; // 0x41
// Version
uint8_t RegVersion; // 0x42
uint8_t RegTestReserved43[0x4B - 0x43]; // 0x43-0x4A
uint8_t RegTcxo; // 0x4B
uint8_t RegTestReserved4C; // 0x4C
uint8_t RegPaDac; // 0x4D
uint8_t RegTestReserved4E[0x5B - 0x4E]; // 0x4E-0x5A
uint8_t RegFormerTemp; // 0x5B
uint8_t RegTestReserved5C[0x61 - 0x5C]; // 0x5C-0x60
// Additional settings
uint8_t RegAgcRef; // 0x61
uint8_t RegAgcThresh1; // 0x62
uint8_t RegAgcThresh2; // 0x63
uint8_t RegAgcThresh3; // 0x64
uint8_t RegTestReserved65[0x70 - 0x65]; // 0x65-0x6F
uint8_t RegPll; // 0x70
}tSX1276LR;
//////////////////////////////////////////////////////////////////////////////
typedef enum
{
Init_LoRa_0_8K,
Init_LoRa_4_8K,
Init_LoRa_10k,
}tSX127xInitPara; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD><C3B6>
typedef enum
{
NORMAL, //<2F><><EFBFBD><EFBFBD>
PARAMETER_INVALID, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
SPI_READCHECK_WRONG, //SPI<50><49><EFBFBD><EFBFBD>
}tSX127xError; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD><C3B6>
typedef enum
{
SLEEP,
STANDBY,
TX_ONGOING,
RX_ONGOING,
}tSX127xState; //<2F><><EFBFBD><EFBFBD>RF<52><46><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD>Բ<EFBFBD>ʹ<EFBFBD><CAB9>
typedef enum
{
HOLDON,
TX,
LISTENING,
}tRadio_Machine; //<2F><><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD>״̬<D7B4><CCAC><EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD>Բ<EFBFBD>ʹ<EFBFBD><CAB9>
typedef enum
{
MASTER,
SLAVE,
}tMasterSlave; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD><C3B6> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
typedef struct
{
tMasterSlave MasterSlave; //<2F><><EFBFBD><EFBFBD>
tSX127xState SX127xState; //<2F><><EFBFBD><EFBFBD>״̬
tRadio_Machine Machine; //<2F>߼<EFBFBD>״̬
}stRadio_Situation; //<2F><><EFBFBD><EFBFBD>״̬<D7B4>ṹ<EFBFBD><E1B9B9>
const unsigned char Freq_Cal_Tab[]=
{
0x75,0x80,0x00,//470MHz
0x75,0xC0,0x00,//471MHz
0x76,0x00,0x00,//472MHz
0x76,0x40,0x00,//473MHz
0x76,0x80,0x00,//474MHz
0x76,0xC0,0x00,//475MHz
0x77,0x00,0x00,//476MHz
0x77,0x40,0x00,//477MHz
0x77,0x80,0x00,//478MHz
0x77,0xC0,0x00,//479MHz
0x78,0x00,0x00,//480MHz
0x78,0x40,0x00,//481MHz
0x78,0x80,0x00,//482MHz
0x78,0xC0,0x00,//483MHz
0x79,0x00,0x00,//484MHz
0x79,0x40,0x00,//485MHz
0x79,0x80,0x00,//486MHz
0x79,0xC0,0x00,//487MHz
0x7A,0x00,0x00,//488MHz
0x7A,0x40,0x00,//489MHz
0x7A,0x80,0x00,//490MHz
0x7A,0xC0,0x00,//491MHz
0x7B,0x00,0x00,//492MHz
0x7B,0x40,0x00,//493MHz
0x7B,0x80,0x00,//494MHz
0x7B,0xC0,0x00,//495MHz
0x7C,0x00,0x00,//496MHz
0x7C,0x40,0x00,//497MHz
0x7C,0x80,0x00,//498MHz
0x7C,0xC0,0x00,//499MHz
0x7D,0x00,0x00,//500MHz
0x7D,0x40,0x00,//501MHz
0x7D,0x80,0x00,//502MHz
0x7D,0xC0,0x00,//503MHz
0x7E,0x00,0x00,//504MHz
0x7E,0x40,0x00,//505MHz
0x7E,0x80,0x00,//506MHz
0x7E,0xC0,0x00,//507MHz
0x7F,0x00,0x00,//508MHz
0x7F,0x40,0x00,//509MHz
0x7F,0x80,0x00,//510MHz
};
//extern stRadio_Situation SX127xSituation;
//===================================<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>===================================================
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46>ʼ<EFBFBD><CABC>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : tSX127xInitPara initPara <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Init_LoRa_0_8K, Init_LoRa_4_8K , Init_LoRa_10k,
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : tSX127xError <20><><EFBFBD><EFBFBD>ö<EFBFBD><C3B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// ˵<><CBB5> : <20><>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD>ʼ<EFBFBD><CABC>Ĭ<EFBFBD><C4AC>Ϊ0<CEAA>ŵ<EFBFBD>
////////////////////////////////////////////////////////////////////////////////
tSX127xError SX127x_init(tSX127xInitPara initPara)
{
uint8_t test = 0;
if(initPara>Init_LoRa_10k) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
{
return PARAMETER_INVALID; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
SX1276Init_IO(); // PAIO<49>ڳ<EFBFBD>ʼ<EFBFBD><CABC>
SX1276Reset(); //<2F><>λRF
//init Regs
SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP );
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP );
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_PACONFIG, 0xff );
SX1276Write( REG_LR_PADAC, RFLR_PADAC_20DBM_ON );
SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US);
SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);
SX1276Write( REG_LR_PAYLOADLENGTH,2);
SX1276Write( REG_LR_MODEMCONFIG3,\
RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON|
RFLR_MODEMCONFIG3_AGCAUTO_ON);
//BW,SF,CR,Header,CRC
// SX1276Write( REG_LR_MODEMCONFIG2,0xFF);
// SX1276Write( REG_LR_SYMBTIMEOUTLSB,0xFF);
switch(initPara){
case Init_LoRa_0_8K:
// SX1276Write( REG_LR_MODEMCONFIG3,\
// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON|
// RFLR_MODEMCONFIG3_AGCAUTO_ON);
SX1276Write( REG_LR_MODEMCONFIG1,\
RFLR_MODEMCONFIG1_BW_125_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\
RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF);
SX1276Write( REG_LR_MODEMCONFIG2,\
RFLR_MODEMCONFIG2_SF_9|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON);
SX1276Write( REG_LR_PREAMBLELSB,10);
SX1276Write(0x31,0x55);
SX1276Read( 0x31,&test);
break;
case Init_LoRa_4_8K:
// SX1276Write( REG_LR_MODEMCONFIG3,\
// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF|
// RFLR_MODEMCONFIG3_AGCAUTO_OFF);
SX1276Write( REG_LR_MODEMCONFIG1,\
RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\
RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF);
SX1276Write( REG_LR_MODEMCONFIG2,\
RFLR_MODEMCONFIG2_SF_8|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON);
// SX1276Write( REG_LR_PREAMBLEMSB,1);
SX1276Write( REG_LR_PREAMBLELSB,10);
break;
case Init_LoRa_10k:
SX1276Read( 0x31,&test);
SX1276Write( 0x31,(test& 0xF8)|0x05);
SX1276Write( 0x37,0x0C);
// SX1276Write( REG_LR_MODEMCONFIG3,\
// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF|
// RFLR_MODEMCONFIG3_AGCAUTO_ON);
SX1276Write( REG_LR_MODEMCONFIG1,\
RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\
RFLR_MODEMCONFIG1_IMPLICITHEADER_ON);
SX1276Write( REG_LR_MODEMCONFIG2,\
RFLR_MODEMCONFIG2_SF_6|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON);
// SX1276Write( REG_LR_PREAMBLEMSB,4);
SX1276Write( REG_LR_PREAMBLELSB,10);
break;
default:
break;
}
if(!LSD_RF_FreqSet(1)) //<2F><><EFBFBD><EFBFBD>Ϊ0<CEAA>ŵ<EFBFBD>
return SPI_READCHECK_WRONG;
return NORMAL;
}
//===================================<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>===================================================
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46>ʼ<EFBFBD><CABC>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : lora_param_t lora <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : tSX127xError <20><><EFBFBD><EFBFBD>ö<EFBFBD><C3B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
////////////////////////////////////////////////////////////////////////////////
tSX127xError SX127x_initLora(lora_param_t *lora)
{
static uint8_t first = 1;
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if(lora->sof != 0xC2 || lora->sf > 6 || (lora->baud != 3 && lora->baud != 5 && lora->baud != 7) || lora->ch > 40 || lora->bw > 9)
return PARAMETER_INVALID;
if(first)
{
first = 0;
SX1276Init_IO(); // PAIO<49>ڳ<EFBFBD>ʼ<EFBFBD><CABC>
}
SX1276Reset(); //<2F><>λRF
//<2F>л<EFBFBD><D0BB><EFBFBD>LoRamode<64><65>standby״̬
SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP );
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP );
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
/*------------------------------------------------
SPI <EFBFBD><EFBFBD>֤ */
uint8_t test = 0;
SX1276Write( REG_LR_HOPPERIOD,0x91 );//ѡһ<D1A1><D2BB><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD>ļĴ<C4BC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֤
SX1276Read( REG_LR_HOPPERIOD,&test);
if(test!=0x91)
return SPI_READCHECK_WRONG;
SX1276Write( REG_LR_PACONFIG, 0xff );
//Frequency Configuration
LSD_RF_FreqSet(lora->ch); //<2F><><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>
//PA Configuration
switch(lora->power)
{
case 0: // 20dBm
LSD_RF_PoutSet(15);
break;
case 1: // 17dBm
LSD_RF_PoutSet(15);
break;
case 2: // 14dBm
LSD_RF_PoutSet(12);
break;
case 3: // 11dBm
LSD_RF_PoutSet(9);
break;
}
SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US);
// <20><>PA Ramp<6D><70>ʱ<EFBFBD>䣬<EFBFBD><E4A3AC><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD>LDO<44><4F><EFBFBD>ܿ<EFBFBD><DCBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD><EFBFBD>PA Rampʱ<70><CAB1>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Rampʱ<70><CAB1><EFBFBD><EFBFBD><EFBFBD>̳<EFBFBD><CCB3><EFBFBD><EFBFBD><EFBFBD>LDO<44><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>TX<54><58><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RF<52>źŲ<C5BA><C5B2><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD>
SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD><D8B1><EFBFBD> Over Current Protection
//PayloadLength <20><>ʼ<EFBFBD><CABC>
SX1276Write( REG_LR_PAYLOADLENGTH, RF_PAYLOAD_LEN);
//ע<>⣬<EFBFBD><E2A3AC>ͷģʽ<C4A3><CABD>Implicit Header<65><72>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD>涨<EFBFBD><E6B6A8><EFBFBD>շ<EFBFBD>˫<EFBFBD><CBAB><EFBFBD><EFBFBD>PL
//BW<42><57>CR<43><52>ImplictHeader_On (SF6) / Off (SF7~12)
SX1276Write( REG_LR_MODEMCONFIG1,\
(((uint8_t)(lora->bw << 4)) | ((uint8_t) ((lora->cr + 1) << 1))) | (lora->sf == 0 ? 0x01 : 0x00));
//SF<53><46>PayloadCrc_Off
SX1276Write( REG_LR_MODEMCONFIG2,\
((uint8_t)((lora->sf + 6) << 4)) | 0x40);
uint8_t temp = 0;
SX1276Read( 0x31,&temp);
if(0 == lora->sf) //<2F><><EFBFBD><EFBFBD>SF = 6<><36><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD><EFBFBD>
{
SX1276Write( 0x31,(temp& 0xF8)|0x05);
SX1276Write( 0x37,0x0C);
}
else
{
SX1276Write( 0x31,(temp& 0xF8)|0x03);
SX1276Write( 0x37,0x0A);
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ż<EFBFBD><C5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>AutoAGCĬ<43>Ͽ<EFBFBD><CFBF><EFBFBD>
// <20><>SF12<31><32>500kHz<48>£<EFBFBD><C2A3><EFBFBD><EFBFBD>뿪<EFBFBD><EBBFAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʺܸ<CABA>
SX1276Write( REG_LR_MODEMCONFIG3,(\
RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON\
)|RFLR_MODEMCONFIG3_AGCAUTO_ON);
// <20><>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
SX1276Write( REG_LR_DIOMAPPING2, RFLR_DIOMAPPING2_DIO4_01);
return NORMAL;
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t*data<74><61><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD>룬uint8_t size<7A><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : <20><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD>ǣ<EFBFBD> preamble<6C>Ļ<EFBFBD>Ĭ<EFBFBD><C4AC>ֵ
////////////////////////////////////////////////////////////////////////////////
void SX1276_TxPacket(uint8_t*data,uint8_t size)
{
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_PREAMBLEMSB,0);
SX1276Write( REG_LR_PREAMBLELSB,8);
SX1276Write( REG_LR_PAYLOADLENGTH,size);
SX1276WriteRxTx(true);
SX1276Write( REG_LR_FIFOADDRPTR,0x80);
SX1276WriteBuffer(REG_LR_FIFO,data,size);
SX1276Write(REG_LR_IRQFLAGS,0xff);
SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE_MASK));
SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 );
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER );
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t clen <20>ɱ<EFBFBD><C9B1><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0>´<EFBFBD>ֵ<EFBFBD><D6B5>Ч<EFBFBD><D0A7><EFBFBD>̶<EFBFBD><CCB6><EFBFBD><EFBFBD>ݰ<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ֵ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>պ<EFBFBD>preamble<6C><65><EFBFBD>û<EFBFBD>Ĭ<EFBFBD><C4AC>ֵΪ
////////////////////////////////////////////////////////////////////////////////
void Rx_mode(uint8_t clen)
{
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_PREAMBLEMSB,0);
SX1276Write( REG_LR_PREAMBLELSB,8);
SX1276Write( REG_LR_PAYLOADLENGTH,clen);
SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE_MASK | RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK));
SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 );
SX1276WriteRxTx(false);
SX1276Write( REG_LR_FIFOADDRPTR,0x00);
SX1276Write(REG_LR_IRQFLAGS,0xff);
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER );
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD>տɱ<D5BF><C9B1><EFBFBD><EFBFBD>ݰ<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t*cbuf<75><66><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>,uint8_t *csize<7A><65><EFBFBD>س<EFBFBD><D8B3><EFBFBD>ָ<EFBFBD><D6B8>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_RxVariPacket(uint8_t*cbuf,uint8_t *csize)
{
uint8_t flag, ptr;
SX1276Read(REG_LR_IRQFLAGS, &flag);
SX1276Read(REG_LR_FIFORXCURRENTADDR, &ptr);
SX1276Read(REG_LR_NBRXBYTES,csize);
SX1276Write( REG_LR_FIFOADDRPTR,ptr);
SX1276ReadFifo(cbuf,*csize);
SX1276Write(REG_LR_IRQFLAGS,0xff);
if(!(flag & RFLR_IRQFLAGS_RXDONE) || (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR))
*csize = 0;
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD>չ̶<D5B9><CCB6><EFBFBD><EFBFBD>ݰ<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t*cbuf<75><66><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>,uint8_t csize<7A><65><EFBFBD>չ̶<D5B9><CCB6><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>10kʱֻ<CAB1>ܲ<EFBFBD><DCB2>ù̶<C3B9><CCB6><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_RxFixiPacket(uint8_t*cbuf,uint8_t *csize)
{
uint8_t flag;
SX1276Read(REG_LR_IRQFLAGS, &flag);
SX1276Write( REG_LR_FIFOADDRPTR,0x00);
SX1276ReadFifo(cbuf,*csize);
SX1276Write(REG_LR_IRQFLAGS,0xff);
if(!(flag & RFLR_IRQFLAGS_RXDONE) || (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR))
*csize = 0;
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD><EFBFBD>standby״̬
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_StandbyMode(void)
{
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD>벻ͬ<EBB2BB>ŵ<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t ch <20><>Χ0-40
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
uint8_t LSD_RF_FreqSet(uint8_t ch)
{
uint8_t test_FRFMSB = 0,test_FRFMID=0,test_FRFLSB=0;
#if 0
SX1276Write( REG_LR_FRFMSB,Freq_Cal_Tab[3*ch]);
SX1276Write( REG_LR_FRFMID,Freq_Cal_Tab[3*ch+1]);
SX1276Write( REG_LR_FRFLSB,Freq_Cal_Tab[3*ch+2]);
SX1276Read(REG_LR_FRFMSB,&test_FRFMSB);
SX1276Read(REG_LR_FRFMID,&test_FRFMID);
SX1276Read(REG_LR_FRFLSB,&test_FRFLSB);
if(test_FRFMSB !=Freq_Cal_Tab[3*ch])
return 0;
if(test_FRFMID !=Freq_Cal_Tab[3*ch+1])
return 0;
if(test_FRFLSB !=Freq_Cal_Tab[3*ch+2])
return 0;
#else
const uint32_t FXOSC = 32000000ul;
float fstep = FXOSC / 524288.0;
uint32_t freq = 470000000ul + ch * 1000000ul;
uint32_t frf = (uint32_t) (freq / fstep + 0.5);
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_FRFMSB, (frf >> 16) & 0xFF);
SX1276Write( REG_LR_FRFMID, (frf >> 8) & 0xFF);
SX1276Write( REG_LR_FRFLSB, (frf & 0xff));
SX1276Read(REG_LR_FRFMSB,&test_FRFMSB);
SX1276Read(REG_LR_FRFMID,&test_FRFMID);
SX1276Read(REG_LR_FRFLSB,&test_FRFLSB);
if(test_FRFMSB != ((frf >> 16) & 0xFF))
return 0;
if(test_FRFMID != ((frf >> 8) & 0xFF))
return 0;
if(test_FRFLSB != (frf & 0xff))
return 0;
#endif
return 1;
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD>ù<EFBFBD><C3B9><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
uint8_t LSD_RF_PoutSet(uint8_t power)
{
LSD_RF_StandbyMode();
SX1276Write( REG_LR_PACONFIG, 0xf0|power);
uint8_t test = 0;
SX1276Read(REG_LR_PACONFIG,&test);
if((0xf0|power)!=test)
return 0;
SX1276Write( REG_LR_PADAC, 0x80|RFLR_PADAC_20DBM_ON );
return 1;
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t*data<74><61><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD>룬uint8_t size<7A><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : <20><><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD>DIO0<4F>ӵ͵<D3B5>ƽ<EFBFBD><C6BD><EFBFBD>ɸߵ<C9B8>ƽ<EFBFBD><C6BD>ÿ<EFBFBD>ε<EFBFBD><CEB5>ô˺<C3B4><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6>Ƚ<EFBFBD>DIO0<4F><30>Ϊ<EFBFBD>ͣ<EFBFBD><CDA3>ȴ<EFBFBD><C8B4>ߵ<EFBFBD>ƽ
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_SendPacket(uint8_t*cbuf,uint8_t csize)
{
unsigned long int j=0xFFFFFF; //<2F><>ʱ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DIO0_IFG_L; //<2F><><EFBFBD><EFBFBD>DIO0<4F><30>־λ
DIO0_IES_L; //<2F><><EFBFBD><EFBFBD>DIO0<4F><30><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD><EFBFBD><EFBFBD>ʽ
DIO0_IE_L; //<2F><>ֹDIO0<4F>ж<EFBFBD>
SX1276_TxPacket(cbuf,csize); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
while((!(DIO0_IFG&DIO0_BIT))&&j)j--; //<2F>ȴ<EFBFBD>GDIO0<4F><30>ƽΪ<C6BD><CEAA>
DIO0_IFG_L; //<2F><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־λ
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t cclen <20>ɱ<EFBFBD><C9B1><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD>̶<EFBFBD><CCB6><EFBFBD><EFBFBD>ݰ<EFBFBD>ʱΪ<CAB1><CEAA><EFBFBD><EFBFBD>ֵ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD>DIO0<4F>ӵ͵<D3B5>ƽ<EFBFBD><C6BD><EFBFBD>ɸߵ<C9B8>ƽ<EFBFBD><C6BD>
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_RXmode(uint8_t cclen)
{
Rx_mode(cclen); //RF<52><46><EFBFBD>ջ<EFBFBD><D5BB>л<EFBFBD><D0BB><EFBFBD>RXģʽ
//SX_DIO0_DIR = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DIO0_IFG_L; //<2F><><EFBFBD><EFBFBD>DIO0<4F><30>־λ
DIO0_IES_L; //<2F><><EFBFBD><EFBFBD>DIO0<4F><30><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD><EFBFBD><EFBFBD>ʽ
DIO0_IE_H; //ʹ<><CAB9>DIO0<4F>ж<EFBFBD>
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD><EFBFBD>Sleep״̬
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : <20><>
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_SleepMode(void)
{
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write(REG_LR_IRQFLAGS,0xff);
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP );
//P1OUT &= ~BIT4; //PA_TX <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0
//P1OUT &= ~BIT5; //PA_TX <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0 Ŀ<><C4BF><EFBFBD>ǽ<EFBFBD><C7BD>ʹ<EFBFBD><CDB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF CAD<41><44>ʼ<EFBFBD><CABC>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : DIO1--CADDetected DIO3---CADDone
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_CADinit(void)
{
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_PREAMBLEMSB,0xf0);
SX1276Write( REG_LR_PREAMBLELSB,0xff);
SX1276Write( REG_LR_IRQFLAGSMASK,\
~(RFLR_IRQFLAGS_CADDONE|RFLR_IRQFLAGS_CADDETECTED));
//
SX1276Write( REG_LR_DIOMAPPING1,\
RFLR_DIOMAPPING1_DIO3_00 | RFLR_DIOMAPPING1_DIO1_10);
SX1276WriteRxTx(false); //set RF switch to RX path
SX1276Write(REG_LR_IRQFLAGS,0xff);
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD><EFBFBD>CAD<41><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ԼΪ(2^SF+32)/BW
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_CAD_Sample(void)
{
SX1276WriteRxTx(false); //set RF switch to RX path
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_CAD );
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : WOR<4F><52>ʼ<EFBFBD><CABC>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : DIO1 :<3A><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> DIO3<4F><33>CAD<41><44>ʱ<EFBFBD>жϣ<D0B6>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ǽ<EFBFBD><C7BD>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD>жϣ<D0B6>
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_WORInit(void)
{
LSD_RF_CADinit(); //CAD<41><44><EFBFBD>ܳ<EFBFBD>ʼ<EFBFBD><CABC>
//CADDoneʹ<65><CAB9>
//SX_DIO3_DIR=0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DIO3_IFG_L; //<2F><><EFBFBD><EFBFBD>DIO3<4F><33>־λ
DIO3_IES_L; //<2F><><EFBFBD><EFBFBD>DIO3<4F><33><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD><EFBFBD><EFBFBD>ʽ
DIO3_IE_H; //DIO3<4F>ж<EFBFBD>
//CADDetectedʹ<64><CAB9>
//SX_DIO1_DIR=0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DIO1_IFG_L; //<2F><><EFBFBD><EFBFBD>DIO1<4F><31>־λ
DIO1_IES_L; //<2F><><EFBFBD><EFBFBD>DIO1<4F><31><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD><EFBFBD><EFBFBD>ʽ
DIO1_IE_H; //ʹ<><CAB9>DIO1<4F>ж<EFBFBD>
//<2F>ر<EFBFBD>DIO0<4F><30><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
DIO0_IE_L; //ʹ<><CAB9>DIO0<4F>ж<EFBFBD>
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : ִ<><D6B4>WOR<4F><52><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t cclen 0<><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˯<EFBFBD>ߡ<EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CAD<41><44><EFBFBD><EFBFBD>ģʽ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_WOR_Execute(uint8_t cclen)
{
switch(cclen)
{
case 0: //<2F><><EFBFBD><EFBFBD>˯<EFBFBD><CBAF>
LSD_RF_SleepMode(); //<2F><><EFBFBD><EFBFBD>˯<EFBFBD><CBAF>ģʽ
ON_Sleep_Timerout(); //<2F><><EFBFBD><EFBFBD>˯<EFBFBD>߳<EFBFBD>ʱ<EFBFBD><CAB1>ʱ<EFBFBD><CAB1>
break;
case 1: //<2F><><EFBFBD><EFBFBD>CAD<41><44><EFBFBD><EFBFBD>ģʽ
OFF_Sleep_Timerout(); //<2F>ر<EFBFBD>˯<EFBFBD>߳<EFBFBD>ʱ<EFBFBD><CAB1>ʱ<EFBFBD><CAB1>
LSD_RF_CAD_Sample(); //<2F><><EFBFBD><EFBFBD>CADһ<44><D2BB>
break;
default: break;
}
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : WOR<4F><52>RX
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : <20><>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> : <20>˳<EFBFBD>WOR<4F><52><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RXģʽ<C4A3><CABD>ǰ<EFBFBD><C7B0>preamble<6C><65>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_WOR_Exit(uint8_t cclen)
{
OFF_Sleep_Timerout();
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_PAYLOADLENGTH,cclen);
SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE));
SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 );
SX1276WriteRxTx(false); //set RF switch to RX path
SX1276Write( REG_LR_FIFOADDRPTR,0x00);
SX1276Write(REG_LR_IRQFLAGS,0xff);
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER );
//SX_DIO0_DIR = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DIO0_IFG_L; //<2F><><EFBFBD><EFBFBD>DIO0<4F><30>־λ
DIO0_IES_L; //<2F><><EFBFBD><EFBFBD>DIO0<4F><30><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD><EFBFBD><EFBFBD>ʽ
DIO0_IE_H; //ʹ<><CAB9>DIO0<4F>ж<EFBFBD>
DIO1_IE_L; //<2F><>ֹDIO1
DIO3_IE_L; //<2F><>ֹDIO3
}
////////////////////////////////////////////////////////////////////////////////
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : RF<52><46><EFBFBD>ͻ<EFBFBD><CDBB>Ѱ<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : uint8_t*data<74><61><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD>룬uint8_t size<7A><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> : <20><>
// ˵<><CBB5> :
////////////////////////////////////////////////////////////////////////////////
void LSD_RF_Awake(uint8_t*cbuf,uint8_t csize)
{
//SX_DIO0_DIR = 0;
DIO0_IFG_L; //<2F><><EFBFBD><EFBFBD>DIO0<4F><30>־λ
DIO0_IES_L; //<2F><><EFBFBD><EFBFBD>DIO0<4F><30><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD><EFBFBD><EFBFBD>ʽ
DIO0_IE_L; //<2F><>ֹDIO0<4F>ж<EFBFBD>
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_PAYLOADLENGTH,csize);
SX1276WriteRxTx(true);
SX1276Write( REG_LR_FIFOADDRPTR,0x80);
SX1276WriteBuffer(REG_LR_FIFO,cbuf,csize);
SX1276Write(REG_LR_IRQFLAGS,0xff);
SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE));
SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 );
SX1276Write( REG_LR_PREAMBLEMSB,0x03);//set preamble length
SX1276Write( REG_LR_PREAMBLELSB,0xEC);//set preamble length
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER );
while((!DIO0_IFG)); //<2F>ȴ<EFBFBD>GDIO0<4F><30>ƽΪ<C6BD><CEAA>
DIO0_IFG_L; //<2F><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־λ
//<2F><><EFBFBD><EFBFBD><EFBFBD>껽<EFBFBD><EABBBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0>󣬽<EFBFBD>ǰ<EFBFBD><C7B0>ʱ<EFBFBD><CAB1><EFBFBD>Ļ<EFBFBD><C4BB><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC>ֵ<EFBFBD><D6B5>
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
SX1276Write( REG_LR_PREAMBLEMSB,0);//set preamble length
SX1276Write( REG_LR_PREAMBLELSB,10);//set preamble length
}
//*****************************************************************************************
#endif