diff --git a/RF-AP/20201015鼎力调通/FR2433-RFSX.h b/RF-AP/20201015鼎力调通/FR2433-RFSX.h new file mode 100644 index 0000000..37a798f --- /dev/null +++ b/RF-AP/20201015鼎力调通/FR2433-RFSX.h @@ -0,0 +1,307 @@ +#ifndef FR2433_RFSX +#define FR2433_RFSX +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: Haybin.Wu@studio +// ļ: +// 汾 V1.0 +// : IAR v6.20 +// : Haybin +// : 2016.05 +// : API for FR4133 +// ޸־ +//////////////////////////////////////////////////////////////////////////////// +#include +#include + +//====================================================================================== +#define CPU_MCLK 8000000 +#define DelayUs(us) __delay_cycles((CPU_MCLK/1000000UL) * us) +#define DelayMs(ms) __delay_cycles((CPU_MCLK/1000UL) * ms) +//////////////////////////////////////////////////////////////////////////////// +//ֻ޸ +//SX1276 SPI I/O definitions +#define SPI_PSEL P1SEL0 +#define SPI_PDIR P1DIR +#define SPI_POUT P1OUT +#define SPI_SI_BIT BIT2 +#define SPI_SO_BIT BIT3 +#define SPI_CLK_BIT BIT1 + +#define SPI_NSS_BIT BIT0 +#define SPI_NSS_PDIR P1DIR +#define SPI_NSS_POUT P1OUT + +//DIO0 +#define DIO0_BIT BIT6 +#define DIO0_DIR P1DIR +#define DIO0_IFG P1IFG +#define DIO0_IES P1IES +#define DIO0_IE P1IE + +//DIO1 +#define DIO1_BIT BIT7 +#define DIO1_DIR P1DIR +#define DIO1_IFG P1IFG +#define DIO1_IES P1IES +#define DIO1_IE P1IE +//DIO3 +#define DIO3_BIT BIT4 +#define DIO3_DIR P2DIR +#define DIO3_IFG P2IFG +#define DIO3_IES P2IES +#define DIO3_IE P2IE +//RST +#define RST_BIT BIT1 +#define RST_PDIR P3DIR +#define RST_POUT P3OUT + +//////////////////////////////////////////////////////////////////////////////// +//SX1276 SPI I/O definitions + +//NSS +#define SPI_NSS_DIR_OUT SPI_NSS_PDIR |= SPI_NSS_BIT //Ƭѡ out +#define SPI_NSS_OUT_1 SPI_NSS_POUT |= SPI_NSS_BIT //1 +#define SPI_NSS_OUT_0 SPI_NSS_POUT &= (~SPI_NSS_BIT) //1 + +//DIO0 +#define DIO0_IFG_H DIO0_IFG |= DIO0_BIT +#define DIO0_IFG_L DIO0_IFG &= ~DIO0_BIT +#define DIO0_IES_H DIO0_IES |= DIO0_BIT +#define DIO0_IES_L DIO0_IES &= ~DIO0_BIT +#define DIO0_IE_H DIO0_IE |= DIO0_BIT +#define DIO0_IE_L DIO0_IE &= ~DIO0_BIT + +//DIO1 +#define DIO1_IFG_H DIO1_IFG |= DIO1_BIT +#define DIO1_IFG_L DIO1_IFG &= ~DIO1_BIT +#define DIO1_IES_H DIO1_IES |= DIO1_BIT +#define DIO1_IES_L DIO1_IES &= ~DIO1_BIT +#define DIO1_IE_H DIO1_IE |= DIO0_BIT +#define DIO1_IE_L DIO1_IE &= ~DIO1_BIT + +//DIO3 +#define DIO3_IFG_H DIO3_IFG |= DIO3_BIT +#define DIO3_IFG_L DIO3_IFG &= ~DIO3_BIT +#define DIO3_IES_H DIO3_IES |= DIO3_BIT +#define DIO3_IES_L DIO3_IES &= ~DIO3_BIT +#define DIO3_IE_H DIO3_IE |= DIO3_BIT +#define DIO3_IE_L DIO3_IE &= ~DIO3_BIT + +//////////////////////////////////////////////////////////////////////////////// +// : SX1276 I/O pins definitions +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Init_IO( void ) +{ + //DIO0ΪP2.0 + //P2DIR &= ~BIT0; + //P2OUT |= BIT0; // Configure DIO0 as pulled-up + //P2REN |= BIT0; // DIO0pull-up register enable + DIO0_DIR&=~DIO0_BIT; + DIO0_IES_L; // DIO0 Hi/Low edge + DIO0_IE_L; // DIO0 interrupt enabled + DIO0_IFG_L; // DIO0IFG cleared + + //DIO1ΪP2.1 + //P2DIR &= ~BIT1; + //P2OUT |= BIT1; // Configure DIO1 as pulled-up + //P2REN |= BIT1; // DIO1pull-up register enable + DIO1_DIR&=~DIO1_BIT; + DIO1_IES_L; // DIO1 Hi/Low edge + DIO1_IE_L; // DIO1 interrupt enabled + DIO1_IFG_L; // DIO1IFG cleared + + //DIO3ΪP2.3 + //P2DIR &= ~BIT3; + //P2OUT |= BIT3; // Configure DIO3 as pulled-up + //P2REN |= BIT3; // DIO3pull-up register enable + DIO3_DIR&=~DIO3_BIT; + DIO3_IES_L; // DIO3 Hi/Low edge + DIO3_IE_L; // DIO3 interrupt enabled + DIO3_IFG_L; // DIO3IFG cleared + + + //SX1276 SPI I/O definitions + // Configure SPI + //SPI SET + SPI_NSS_DIR_OUT; + SPI_NSS_OUT_1; // /CS disable + + // SPI option select + SPI_PSEL |= SPI_SI_BIT+SPI_SO_BIT+SPI_CLK_BIT; + + UCB0CTLW0 |= UCSWRST; // **Put state machine in reset** + UCB0CTLW0 |= UCMST|UCSYNC|UCCKPH|UCMSB; // 3-pin, 8-bit SPI master + // Clock polarity high, MSB + UCB0CTLW0 |= UCSSEL__SMCLK; // SMCLK + UCB0BR0 = 1; // /2,fBitClock = fBRCLK/(UCBRx+1). + UCB0BR1 = 0; // + UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** + + //SX1276 RESET I/O definitions + RST_PDIR |= RST_BIT; + RST_POUT |= RST_BIT; + +} + +//////////////////////////////////////////////////////////////////////////////// +// : ˯߳ʱʱ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void ON_Sleep_Timerout(void) +{ + + //Timer1_A3 setup + TA1R =0; //ʱ + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768; + TA0CTL |= TASSEL_1 | MC_1; //ʱʱ +} +//////////////////////////////////////////////////////////////////////////////// +// : ر˯߳ʱʱ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void OFF_Sleep_Timerout(void) +{ + //TA0R =0; //ʱ + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768; + TA0CTL = TASSEL_1 | MC_0; //رնʱ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF λ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Reset(void) +{ + RST_POUT &= ~RST_BIT; //ӲλIO0 + DelayMs(6); //ʱ + RST_POUT |= RST_BIT; //Ϊ1 + DelayMs(5); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ +// : uint8_t addr,Ĵַ uint8_t *buffer,ָ uint8_t sizeָ볤 +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +{ + uint8_t i; + SPI_PSEL |= SPI_SO_BIT;//SPIbugĹ쳣 + SPI_NSS_OUT_0; +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + UCB0IFG &= ~UCRXIFG; // Clear flag + UCB0TXBUF = (addr | 0x80); // Send address + while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish + UCB0IFG &= ~UCTXIFG; // Clear flag + for( i = 0; i < size; i++ ) + { + UCB0TXBUF = buffer[i]; // Send data + while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish + UCB0IFG &= ~UCTXIFG; + } +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + SPI_NSS_OUT_1; + SPI_PSEL &= ~SPI_SO_BIT;//SPIbugĹ쳣 +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ +// : uint8_t addr,Ĵַ uint8_t *buffer,洢ָ uint8_t sizeҪij +// ز : ݷص*buffer +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +{ + uint8_t i; + SPI_PSEL |= SPI_SO_BIT;//SPIbugĹ쳣 + SPI_NSS_OUT_0; +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + UCB0IFG &= ~UCRXIFG; // Clear flag + UCB0TXBUF = (addr & 0x7F); // Send address + while (!(UCB0IFG&UCTXIFG)); // Wait for end of addr byte TX + UCB0IFG &= ~UCTXIFG; // Clear flag + for( i = 0; i < size; i++ ) + { + UCB0TXBUF = 0; //Initiate next data RX + while (!(UCB0IFG&UCRXIFG)); // Wait for RX to finish + buffer[i] = UCB0RXBUF; // Store data from last data RX + //ȡUCB0RXBUFIFGԶReset + } +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + SPI_NSS_OUT_1; + SPI_PSEL &= ~SPI_SO_BIT;//SPIbugĹ쳣 + UCB0IFG=0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַд1ֽ +// : uint8_t addr,Ĵַ uint8_t data +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Write( uint8_t addr, uint8_t data ) +{ + SX1276WriteBuffer( addr, &data, 1 ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ1ֽ +// : uint8_t addr,Ĵַ uint8_t *dataݴ洢ַ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Read( uint8_t addr, uint8_t *data ) +{ + SX1276ReadBuffer( addr, data, 1 ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF FIFOд +// : uint8_t *buffer,ָ uint8_t size +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteFifo( uint8_t *buffer, uint8_t size ) +{ + SX1276WriteBuffer( 0, buffer, size ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF FIFO +// : uint8_t *buffer,ָ uint8_t size +// ز : uint8_t *buffer 洢ȡ +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276ReadFifo( uint8_t *buffer, uint8_t size ) +{ + SX1276ReadBuffer( 0, buffer, size ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF TX/RXPAл +// : bool txEnable л߼ +// ز : +// ˵ :棺ΪTX٣ΪRX ΪӲPAIO +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteRxTx( bool txEnable ) +{ + if( txEnable != 0 ) //Ϊ棬ΪTX + { + ; + } + else //Ϊ٣ΪRX + { + ; + } +} + +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/20201015鼎力调通/RF-Module.c b/RF-AP/20201015鼎力调通/RF-Module.c new file mode 100644 index 0000000..8b373e2 --- /dev/null +++ b/RF-AP/20201015鼎力调通/RF-Module.c @@ -0,0 +1,525 @@ +// Haybin_Wu +// Shenitech-RD +// 2016.5 +// Built with IAR Embedded Workbench v6.2 +//****************************************************************************** +// Modify by Qian Xianghong +// 2020.10 +// ޸־ģɴںRF˫͸ģʽ +//****************************************************************************** +#include +#include +#include +#include +#include "FR2433-RFSX.h" +#include "RF_SX1276.h" + +// Ƶò +lora_param_t Lora_Param; + +#define TRAN_BUF_SIZE (1024) + +// UA1ӡ +char printBuf[200]; +void uart_print() +{ +#if 0 // ӡڵ2MD0MD1ģʽѡ + char *p = printBuf; + while(*p) + { + if(*p == '\n') // ǰӻس + { + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = '\r'; + } + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = *p++; + } +#endif +} + +// ɱĺ궨 +#define PRINTF(format, ...) \ +{ \ + snprintf(printBuf, sizeof(printBuf), format, ##__VA_ARGS__); \ + uart_print(); \ +} + +// UA0λݵbuf +uint8_t UA0_RxBuf[TRAN_BUF_SIZE] = {0}; +uint16_t UA0_RxBuf_Length = 0; +uint16_t UA0_RxBuf_offset = 0; +// UA0ճʱ +volatile uint8_t UA0_Rx_Timeout = 1; + +// RFݵbuf +uint8_t RF_RxBuf[TRAN_BUF_SIZE] = {0}; +uint16_t RF_RxBuf_Length = 0; +uint16_t RF_RxBuf_offset = 0; +// RFճʱ־ +volatile uint8_t RF_Rx_Timeout = 1; + +//////////////////////////////////////////////////////////////////////////////// +// ڳʼ +void UA0_Init(uint32_t baudrate) +{ + // Configure UART + UCA0CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + if(baudrate == 115200) + { + UCA0BR0 = 4; // 8000000/16/115200//λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.44444 + UCA0MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢Baud Rate + } + else if(baudrate == 38400) + { + UCA0BR0 = 13; // 8000000/16/38400 /λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.33333 + UCA0MCTLW = 0x8400 | UCOS16 | UCBRF_0;//΢Baud Rate + } + else + { + UCA0BR0 = 52; // 8000000/16/9600 /λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.33333 + UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1;//΢Baud Rate + } + UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt +} + +// Ӧ +void UA0_Response(char *s) +{ + while(*s) + { + while(!(UCA0IFG & UCTXIFG)); + UCA0TXBUF = *s++; + } + // ȴͽ + while(!(UCA0IFG & UCTXCPTIFG)); + DelayMs(2); +} + +//////////////////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////////////////// + int main(void) +{ + uint8_t sendCh; + uint8_t sf = 6, bw = 9, cr = 0, ch = 9; + + WDTCTL = (WDTPW | WDTHOLD); // Stop WDT + // Port Configuration all un-used pins to output low + P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; + P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; + PM5CTL0 &= ~LOCKLPM5;//Ź + + // Configure DCO Clock + //ⲿʱԴ + P2SEL0 |= (BIT0 | BIT1); // set XT1 pin as second function + do + { + CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag + SFRIFG1 &= ~OFIFG; + } while (SFRIFG1 & OFIFG); // Test oscillator fault flag + //־ڽ͹ + + __bis_SR_register(SCG0); // disable FLL + CSCTL3 |= SELREF__XT1CLK; // ⲿ 32768hz reference source + CSCTL0 = 0; // clear DCO and MOD registers + CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first + CSCTL1 |= DCORSEL_3; //DCO=8Mhz + CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz + __delay_cycles(3); + __bic_SR_register(SCG0); // enable FLL + while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked + + CSCTL4 = SELREF__XT1CLK + SELMS__DCOCLKDIV;// set XT1CLK(32768Hz) as ACLK source & MCLK/SMCLK=DCO + + //Timer0_A0 setup + TA0CCTL0 = CCIE; // TACCR0 interrupt enabled + TA0CCR0 = 32768 / 32; // ڽճʱ: 1000/32=31.25ms + TA0CTL = MC__STOP | TACLR; // Stop mode, Clear counter + + //Timer1_A0 setup + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768 / 4; // RFճʱ: 1000/4=250ms + TA1CTL = MC__STOP | TACLR; // Stop mode, Clear counter + + // ģȱʡ + Lora_Param.sof = 0xC2; + Lora_Param.addr = 0xADF2; // ͨŵַ0xADF2 + Lora_Param.sf = sf; // sf=12 + Lora_Param.baud = 7; // 9600 + Lora_Param.cr = cr; // cr=4/8 + Lora_Param.ch = ch; // 479MHz + Lora_Param.power = 1; // 17dBm + Lora_Param.bw = bw; // 500kHz + Lora_Param.unicast = 0; // unicast off + + // Configure UART pins + P1SEL1 &= ~(BIT4 | BIT5); // set 2-UART pin as second function + P1SEL0 |= (BIT4 | BIT5); // set 2-UART pin as second function + if(Lora_Param.baud == 7) + UA0_Init(115200); + else if(Lora_Param.baud == 5) + UA0_Init(38400); + else + UA0_Init(9600); + +#if 0 // ӡ + // Configure UART pins + P2SEL1 &= ~(BIT5 | BIT6); // set 2-UART pin as second function + P2SEL0 |= (BIT5 | BIT6); // set 2-UART pin as second function + // Configure UART + UCA1CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + UCA1BR0 = 4; // 8000000/16/115200//λ16 UCOS16λҪλ + UCA1BR1 = 0; // Fractional portion = 0.44444 + UCA1MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢Baud Rate + UCA1CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt + + // ӡλԭ(Դ𣬲Ź) + PRINTF("\nModule reseted: %04X\n", PMMIFG); + +#else // MD0MD1ģʽ + P2SEL1 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO + P2SEL0 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO + P2DIR &= ~(BIT5 | BIT6); // Input + P2REN |= (BIT5 | BIT6); // enable pull + P2OUT &= ~(BIT5 | BIT6); // pull-down + + P2DIR |= BIT3; // Output + P2OUT |= BIT3; // Output high +#endif + + _EINT(); + + // ӡλԭ(Դ𣬲Ź) +// RF_RxBuf[0] = PMMIFG >> 8; +// RF_RxBuf[1] = PMMIFG & 0xFF; +// RF_RxBuf_Length = 2; +// RF_RxBuf_offset = 0; +// UCA0IE |= UCTXIE; +// while(UCA0IE & UCTXIE); + + // Ĵλԭ + SYSRSTIV; + + //ģԻ + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; //ģʼʧܸλ + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + // ʼڽģʽ + LSD_RF_RXmode(RF_PAYLOAD_LEN); + // ĬϷŵ + sendCh = Lora_Param.ch; + + // Ź: ʱʱΪ2^27/SMCLK8000000ƵԼΪ16s + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + while(1) + { +#if 0 +// for(cr = 0; cr <= 3; cr++) + { + for(ch = 0; ch <= 40; ch++) + { + // TODO: ι + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + // Ͳ + RF_RxBuf[0] = cr; + RF_RxBuf[1] = ch; + RF_RxBuf_Length = 2; + RF_RxBuf_offset = 0; + UCA0IE |= UCTXIE; + while(UCA0IE & UCTXIE); + + // ͱ + Lora_Param.cr = cr; + Lora_Param.ch = ch; + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; //ģʼʧܸλ + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + UA0_RxBuf_offset = UA0_RxBuf_Length; + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + + RF_RxBuf[0] = Lora_Param.sf; + RF_RxBuf[1] = Lora_Param.bw; + RF_RxBuf_Length = 2; + RF_RxBuf_offset = 0; + UCA0IE |= UCTXIE; + while(UCA0IE & UCTXIE); + + // ӳ3 + DelayMs(4000); + } + } +#else +#if 1 + // TODO: ι + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + // ģʽ + if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6)) + { + if(UA0_RxBuf_Length - UA0_RxBuf_offset >= 6) + { + P2OUT &= ~BIT3; // Output low + + if(UA0_RxBuf[0] == 0xC2) + { + // + memmove(&Lora_Param, UA0_RxBuf, sizeof(Lora_Param)); + Lora_Param.addr = (UA0_RxBuf[1] << 8) | UA0_RxBuf[2]; + + //ģԻ + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; //ģʼʧܸλ + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + // Ĭϴڽģʽ + LSD_RF_RXmode(RF_PAYLOAD_LEN); + // ĬϷŵ + sendCh = Lora_Param.ch; + // Ӧ + UA0_Response("OK\r\n"); + + // ı䴮ڲ + if(Lora_Param.baud == 7) + UA0_Init(115200); + else if(Lora_Param.baud == 5) + UA0_Init(38400); + else + UA0_Init(9600); + } + UA0_RxBuf_offset += 6; + + P2OUT |= BIT3; // Output high + } + } + // ͸ģʽ + else if((P2IN & (BIT5 | BIT6)) == 0) +#endif + { + if(UA0_RxBuf_Length > UA0_RxBuf_offset) + { + // 㴫䣬ָŵ + if(Lora_Param.unicast && UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 3) + sendCh = UA0_RxBuf[2]; + + if(UA0_RxBuf_Length - UA0_RxBuf_offset >= RF_PAYLOAD_LEN) + { + LSD_RF_FreqSet(sendCh); + LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, RF_PAYLOAD_LEN); + UA0_RxBuf_offset += RF_PAYLOAD_LEN; + PRINTF("Send packet\n"); + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + } + else if(UA0_Rx_Timeout) + { + LSD_RF_FreqSet(sendCh); + LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, UA0_RxBuf_Length - UA0_RxBuf_offset); + UA0_RxBuf_offset = UA0_RxBuf_Length; + PRINTF("Send packet\n"); + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + } + } + } +#endif + } +} + +// Port 1 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=PORT1_VECTOR +__interrupt void Port_1(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(PORT1_VECTOR))) Port_1 (void) +#else +#error Compiler not supported! +#endif +{ + uint8_t offset = 0; + uint8_t len[1] = {0}; + uint8_t buf[RF_PAYLOAD_LEN]; + if(DIO0_IFG&DIO0_BIT) //ݴжϴ + { + // ж + DIO0_IFG &= ~DIO0_BIT; + + // ȡRF + LSD_RF_RxVariPacket(buf, len); //տɱݰΪʣֻýչ̶ݰ + + if(len[0] == 0) + return; + + TA1CTL = MC__STOP | TACLR; // ֹͣʱλ + TA1CTL = TASSEL__ACLK | MC__UP; // ¿ʼʱ + + offset = 0; + if(RF_Rx_Timeout) // µһݵ + { + RF_Rx_Timeout = 0; + + // λ + RF_RxBuf_Length = 0; + RF_RxBuf_offset = 0; + + if(Lora_Param.unicast) + { + // 㴫䣬ַŵУʧ + if(len[0] <= 3 || buf[2] != Lora_Param.ch || ((buf[0] << 8) | buf[1]) != Lora_Param.addr) + return; + // ǰ3ַ + offset = 3; + len[0] -= offset; + } + } + + PRINTF("Recv packet\n"); + + // ͸ģʽ + if((P2IN & (BIT5 | BIT6)) == 0) + { + if(RF_RxBuf_Length + len[0] <= TRAN_BUF_SIZE) + { + memmove(RF_RxBuf + RF_RxBuf_Length, buf + offset, len[0]); + // жϷʽ򴮿ת + RF_RxBuf_Length += len[0]; + UCA0IE |= UCTXIE; + } + } + } +} + +// Timer0 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER0_A0_VECTOR +__interrupt void Timer0_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) Timer0_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ֹͣʱλ + TA0CTL = MC__STOP | TACLR; + // ڽճʱ + UA0_Rx_Timeout = 1; +} + +// Timer1 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER1_A0_VECTOR +__interrupt void Timer1_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER1_A0_VECTOR))) Timer1_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ֹͣʱλ + TA1CTL = MC__STOP | TACLR; + // RFճʱ + RF_Rx_Timeout = 1; +} + +// UAR0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=USCI_A0_VECTOR +__interrupt void USCI_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ж + if((UCA0IE & UCRXIE) && (UCA0IFG & UCRXIFG)) + { + uint8_t c = UCA0RXBUF; + + TA0CTL = MC__STOP | TACLR; // ֹͣʱλ + TA0CTL = TASSEL__ACLK | MC__UP; // ¿ʼʱ + + if(UA0_Rx_Timeout) // µһݵ + { + UA0_Rx_Timeout = 0; + // λ + UA0_RxBuf_Length = 0; + UA0_RxBuf_offset = 0; + } + + if(UA0_RxBuf_Length < TRAN_BUF_SIZE) + { +#if 1 + // ģʽ + if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6)) + { + // 1ַΪ0xC2 + if(UA0_RxBuf_Length > 0 || c == 0xC2) + UA0_RxBuf[UA0_RxBuf_Length++] = c; + } + // ͸ģʽ + else if((P2IN & (BIT5 | BIT6)) == 0) +#endif + { + // ͸ + UA0_RxBuf[UA0_RxBuf_Length++] = c; + } + } + } + + // ж + if((UCA0IE & UCTXIE) && (UCA0IFG & UCTXIFG)) + { + UCA0TXBUF = RF_RxBuf[RF_RxBuf_offset++]; // ַ + if(RF_RxBuf_offset >= RF_RxBuf_Length) // ȫ + { + // ֹж + UCA0IE &= ~UCTXIE; + } + } +} diff --git a/RF-AP/20201015鼎力调通/RF_SX1276.h b/RF-AP/20201015鼎力调通/RF_SX1276.h new file mode 100644 index 0000000..264686b --- /dev/null +++ b/RF-AP/20201015鼎力调通/RF_SX1276.h @@ -0,0 +1,1333 @@ +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: Haybin.Wu@studio +// ļ: +// 汾 V1.0 +// : IAR v6.20 +// : Haybin +// : 2016.05 +// : API +// ޸־ +//////////////////////////////////////////////////////////////////////////////// +// Modify by Qian Xianghong +// 2020.10 +// ޸־ +// 1. LSD_RF_SendPacket(): +// ޸жDIO0־ȷɣúʱ +// 2. LSD_RF_RXmode(): +// PayloadCrcErrorʶ +// 3. LSD_RF_RxVariPacket(): +// жRxDonePayloadCRCErrorʶ +// ȶȡREG_LR_FIFORXCURRENTADDRĴֵٴӸõַʼȡݡ +// 4. LSD_RF_RxFixiPacket(): +// жRxDonePayloadCRCErrorʶ +// 5. SX127x_initLora()ڸسʼLoRa +//////////////////////////////////////////////////////////////////////////////// +#include +#include +#include "FR2433-RFSX.h" +#ifndef RF_SX1276 +#define RF_SX1276 + +uint8_t LSD_RF_FreqSet(uint8_t ch); +uint8_t LSD_RF_PoutSet(uint8_t power); +//====================================================================================== +#define RF_PAYLOAD_LEN (64) + +#pragma pack(push, 1) +// LORAҫ +typedef struct +{ + uint8_t sof; // ǰ룬̶Ϊ0xC2 + uint16_t addr; // ͨŵַ + unsigned char sf : 3; // Ƶ: 0-1-7,...,6-12,7- + unsigned char baud : 3; // ڲʣ3-9600,7-115200, ౣ + unsigned char cr : 2; // : 0-4/5,1-4/6,2-4/7,3-4/8 + uint8_t ch; // ͨŵ: 0~40(470M~510M),ౣ + unsigned char power : 2; // Power: 0-20dBm,1-17dBm,2-14dBm,3-11dBm + unsigned char : 1; + unsigned char bw : 4; // 0-7.8kHz,1-10.4kHz,...,9-500kHz, ౣ + unsigned char unicast : 1; // Ƿ񶨵㷢 +} lora_param_t; +#pragma pack(pop) +//====================================================================================== +/*! + * SX1276 LoRa General parameters definition + */ +typedef struct sLoRaSettings +{ + uint32_t RFFrequency; + int8_t Power; + uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz, + // 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved] + uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips] + uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + bool CrcOn; // [0: OFF, 1: ON] + bool ImplicitHeaderOn; // [0: OFF, 1: ON] + bool RxSingleOn; // [0: Continuous, 1 Single] + bool FreqHopOn; // [0: OFF, 1: ON] + uint8_t HopPeriod; // Hops every frequency hopping period symbols + uint32_t TxPacketTimeout; + uint32_t RxPacketTimeout; + uint8_t PayloadLength; +}tLoRaSettings; + +/*! + * RF packet definition + */ +#define RF_BUFFER_SIZE_MAX 128 +#define RF_BUFFER_SIZE 80 + +/*! + * RF state machine + */ +//LoRa +typedef enum +{ + RFLR_STATE_IDLE, + RFLR_STATE_RX_INIT, + RFLR_STATE_RX_RUNNING, + RFLR_STATE_RX_DONE, + RFLR_STATE_RX_TIMEOUT, + RFLR_STATE_TX_INIT, + RFLR_STATE_TX_RUNNING, + RFLR_STATE_TX_DONE, + RFLR_STATE_TX_TIMEOUT, + RFLR_STATE_CAD_INIT, + RFLR_STATE_CAD_RUNNING, +}tRFLRStates; + +/*! + * SX1276 definitions + */ +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +/*! + * SX1276 Internal registers Address + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +//#define REG_LR_BANDSETTING 0x04 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_NBRXBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 + +/*! + * SX1276 LoRa bit control definition + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegBandSetting + */ +#define RFLR_BANDSETTING_MASK 0x3F +#define RFLR_BANDSETTING_AUTO 0x00 // Default +#define RFLR_BANDSETTING_DIV_BY_1 0x40 +#define RFLR_BANDSETTING_DIV_BY_2 0x80 +#define RFLR_BANDSETTING_DIV_BY_6 0xC0 + + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RFLR_LNA_BOOST_LF_GAIN 0x08 +#define RFLR_LNA_BOOST_LF_IP3 0x10 +#define RFLR_LNA_BOOST_LF_BOOST 0x18 +#define RFLR_LNA_RXBANDFORCE_MASK 0xFB +#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + + + +/*! + * RegFifoRxNbBytes (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueMsb (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueLsb (Read Only) // + */ + + +/*! + * RegRxPacketCntValueMsb (Read Only) // + */ + + + /*! + * RegRxPacketCntValueLsb (Read Only) // + */ + + + /*! + * RegModemStat (Read Only) // + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) // + */ + + + /*! + * RegPktRssiValue (Read Only) // + */ + + +/*! + * RegRssiValue (Read Only) // + */ + + + /*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F + +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + + /*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + + +/*! + * RegHopChannel (Read Only) + */ + +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40 +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegModemConfig3 + */ +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +/*! + * RegFormerTemp + */ + +typedef struct sSX1276LR +{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + + uint8_t RegTestReserved02[0x06 - 0x02]; // 0x02-0x05 + // uint8_t RegRes02; // 0x02 + // uint8_t RegRes03; // 0x03 + // uint8_t RegBandSetting; // 0x04 + // uint8_t RegRes05; // 0x05 + + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + // LoRa registers + uint8_t RegFifoAddrPtr; // 0x0D + uint8_t RegFifoTxBaseAddr; // 0x0E + uint8_t RegFifoRxBaseAddr; // 0x0F + uint8_t RegFifoRxCurrentAddr; // 0x10 + uint8_t RegIrqFlagsMask; // 0x11 + uint8_t RegIrqFlags; // 0x12 + uint8_t RegNbRxBytes; // 0x13 + uint8_t RegRxHeaderCntValueMsb; // 0x14 + uint8_t RegRxHeaderCntValueLsb; // 0x15 + uint8_t RegRxPacketCntValueMsb; // 0x16 + uint8_t RegRxPacketCntValueLsb; // 0x17 + uint8_t RegModemStat; // 0x18 + uint8_t RegPktSnrValue; // 0x19 + uint8_t RegPktRssiValue; // 0x1A + uint8_t RegRssiValue; // 0x1B + uint8_t RegHopChannel; // 0x1C + uint8_t RegModemConfig1; // 0x1D + uint8_t RegModemConfig2; // 0x1E + uint8_t RegSymbTimeoutLsb; // 0x1F + uint8_t RegPreambleMsb; // 0x20 + uint8_t RegPreambleLsb; // 0x21 + uint8_t RegPayloadLength; // 0x22 + uint8_t RegMaxPayloadLength; // 0x23 + uint8_t RegHopPeriod; // 0x24 + uint8_t RegFifoRxByteAddr; // 0x25 + uint8_t RegModemConfig3; // 0x26 + uint8_t RegTestReserved27[0x31 - 0x27]; // 0x27-0x30 + //void SX1276LoRaSetNbTrigPeaks( uint8_t value )õ + uint8_t RegTestReserved31; // 0x31 + uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x3F + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + + uint8_t RegTestReserved43[0x4B - 0x43]; // 0x43-0x4A + uint8_t RegTcxo; // 0x4B + uint8_t RegTestReserved4C; // 0x4C + uint8_t RegPaDac; // 0x4D + uint8_t RegTestReserved4E[0x5B - 0x4E]; // 0x4E-0x5A + uint8_t RegFormerTemp; // 0x5B + uint8_t RegTestReserved5C[0x61 - 0x5C]; // 0x5C-0x60 + // Additional settings + uint8_t RegAgcRef; // 0x61 + uint8_t RegAgcThresh1; // 0x62 + uint8_t RegAgcThresh2; // 0x63 + uint8_t RegAgcThresh3; // 0x64 + uint8_t RegTestReserved65[0x70 - 0x65]; // 0x65-0x6F + uint8_t RegPll; // 0x70 +}tSX1276LR; +////////////////////////////////////////////////////////////////////////////// +typedef enum +{ + Init_LoRa_0_8K, + Init_LoRa_4_8K, + Init_LoRa_10k, +}tSX127xInitPara; //ö + +typedef enum +{ + NORMAL, // + PARAMETER_INVALID, // + SPI_READCHECK_WRONG, //SPI +}tSX127xError; //ö + +typedef enum +{ + SLEEP, + STANDBY, + TX_ONGOING, + RX_ONGOING, +}tSX127xState; //RF״̬ûԲʹ + +typedef enum +{ + HOLDON, + TX, + LISTENING, +}tRadio_Machine; //߼״̬ûԲʹ + +typedef enum +{ + MASTER, + SLAVE, +}tMasterSlave; //ö ʱ + +typedef struct +{ + tMasterSlave MasterSlave; // + tSX127xState SX127xState; //״̬ + tRadio_Machine Machine; //߼״̬ +}stRadio_Situation; //״̬ṹ + +const unsigned char Freq_Cal_Tab[]= +{ + 0x75,0x80,0x00,//470MHz + 0x75,0xC0,0x00,//471MHz + 0x76,0x00,0x00,//472MHz + 0x76,0x40,0x00,//473MHz + 0x76,0x80,0x00,//474MHz + 0x76,0xC0,0x00,//475MHz + 0x77,0x00,0x00,//476MHz + 0x77,0x40,0x00,//477MHz + 0x77,0x80,0x00,//478MHz + 0x77,0xC0,0x00,//479MHz + 0x78,0x00,0x00,//480MHz + 0x78,0x40,0x00,//481MHz + 0x78,0x80,0x00,//482MHz + 0x78,0xC0,0x00,//483MHz + 0x79,0x00,0x00,//484MHz + 0x79,0x40,0x00,//485MHz + 0x79,0x80,0x00,//486MHz + 0x79,0xC0,0x00,//487MHz + 0x7A,0x00,0x00,//488MHz + 0x7A,0x40,0x00,//489MHz + 0x7A,0x80,0x00,//490MHz + 0x7A,0xC0,0x00,//491MHz + 0x7B,0x00,0x00,//492MHz + 0x7B,0x40,0x00,//493MHz + 0x7B,0x80,0x00,//494MHz + 0x7B,0xC0,0x00,//495MHz + 0x7C,0x00,0x00,//496MHz + 0x7C,0x40,0x00,//497MHz + 0x7C,0x80,0x00,//498MHz + 0x7C,0xC0,0x00,//499MHz + 0x7D,0x00,0x00,//500MHz + 0x7D,0x40,0x00,//501MHz + 0x7D,0x80,0x00,//502MHz + 0x7D,0xC0,0x00,//503MHz + 0x7E,0x00,0x00,//504MHz + 0x7E,0x40,0x00,//505MHz + 0x7E,0x80,0x00,//506MHz + 0x7E,0xC0,0x00,//507MHz + 0x7F,0x00,0x00,//508MHz + 0x7F,0x40,0x00,//509MHz + 0x7F,0x80,0x00,//510MHz +}; + +//extern stRadio_Situation SX127xSituation; +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : tSX127xInitPara initPara Init_LoRa_0_8K, Init_LoRa_4_8K , Init_LoRa_10k, +// ز : tSX127xError ö +// ˵ : ʼʱŵʼĬΪ0ŵ +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_init(tSX127xInitPara initPara) +{ + uint8_t test = 0; + if(initPara>Init_LoRa_10k) // + { + return PARAMETER_INVALID; // + } + SX1276Init_IO(); // PAIOڳʼ + SX1276Reset(); //λRF + //init Regs + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PACONFIG, 0xff ); + SX1276Write( REG_LR_PADAC, RFLR_PADAC_20DBM_ON ); + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US); + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA); + SX1276Write( REG_LR_PAYLOADLENGTH,2); + SX1276Write( REG_LR_MODEMCONFIG3,\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON| + RFLR_MODEMCONFIG3_AGCAUTO_ON); + //BW,SF,CR,Header,CRC +// SX1276Write( REG_LR_MODEMCONFIG2,0xFF); +// SX1276Write( REG_LR_SYMBTIMEOUTLSB,0xFF); + switch(initPara){ + case Init_LoRa_0_8K: +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON| +// RFLR_MODEMCONFIG3_AGCAUTO_ON); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_125_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_9|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); + SX1276Write( REG_LR_PREAMBLELSB,10); + SX1276Write(0x31,0x55); + SX1276Read( 0x31,&test); + break; + case Init_LoRa_4_8K: +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF| +// RFLR_MODEMCONFIG3_AGCAUTO_OFF); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_8|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); +// SX1276Write( REG_LR_PREAMBLEMSB,1); + SX1276Write( REG_LR_PREAMBLELSB,10); + break; + case Init_LoRa_10k: + SX1276Read( 0x31,&test); + SX1276Write( 0x31,(test& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF| +// RFLR_MODEMCONFIG3_AGCAUTO_ON); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_ON); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_6|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); +// SX1276Write( REG_LR_PREAMBLEMSB,4); + SX1276Write( REG_LR_PREAMBLELSB,10); + break; + default: + break; + } + if(!LSD_RF_FreqSet(1)) //Ϊ0ŵ + return SPI_READCHECK_WRONG; + + return NORMAL; +} + +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : lora_param_t lora +// ز : tSX127xError ö +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_initLora(lora_param_t *lora) +{ + float BandWidthKHz = 500.0;//ؼSymbolʹ + float TsXms = 1.024;//1.024ms + + // + if(lora->sof != 0xC2 || lora->sf > 6 || (lora->baud != 3 && lora->baud != 5 && lora->baud != 7) || lora->ch > 40 || lora->bw > 9) + return PARAMETER_INVALID; + + //BandWidth + switch(lora->bw) + { + case 9: + BandWidthKHz = 500.0; + break; + case 8: + BandWidthKHz = 250.0; + break; + case 7: + BandWidthKHz = 125.0; + break; + case 6: + BandWidthKHz = 62.5; + break; + case 5: + BandWidthKHz = 41.66; + break; + case 4: + BandWidthKHz = 31.25; + break; + case 3: + BandWidthKHz = 20.83; + break; + case 2: + BandWidthKHz = 15.62; + break; + case 1: + BandWidthKHz = 10.41; + break; + case 0: + BandWidthKHz = 7.81; + break; + } + //LoRaԪڣλms + TsXms = (2 << (lora->sf + 6 - 1)) / BandWidthKHz; + + SX1276Init_IO(); // PAIOڳʼ + SX1276Reset(); //λRF + + //лLoRamodestandby״̬ + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + + /*------------------------------------------------ + SPI ֤ */ + uint8_t test = 0; + SX1276Write( REG_LR_HOPPERIOD,0x91 );//ѡһòļĴ֤ + SX1276Read( REG_LR_HOPPERIOD,&test); + if(test!=0x91) + return SPI_READCHECK_WRONG; + + SX1276Write( REG_LR_PACONFIG, 0xff ); + + //Frequency Configuration + LSD_RF_FreqSet(lora->ch); //Ƶ + //PA Configuration + switch(lora->power) + { + case 0: // 20dBm + LSD_RF_PoutSet(15); + break; + case 1: // 17dBm + LSD_RF_PoutSet(15); + break; + case 2: // 14dBm + LSD_RF_PoutSet(12); + break; + case 3: // 11dBm + LSD_RF_PoutSet(9); + break; + } + + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US); + // PA Rampʱ䣬ûLDOܿʵPA Rampʱ + // Rampʱ̳LDOʱֽTXϵͳΪRFźŲֵ + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);//ر Over Current Protection + + //PayloadLength ʼ + SX1276Write( REG_LR_PAYLOADLENGTH, RF_PAYLOAD_LEN); + //ע⣬ͷģʽImplicit Headerʱǰ涨շ˫PL + + //BWCRImplictHeader_On (SF6) / Off (SF7~12) + SX1276Write( REG_LR_MODEMCONFIG1,\ + (((uint8_t)(lora->bw << 4)) | ((uint8_t) ((lora->cr + 1) << 1))) | (lora->sf == 0 ? 0x01 : 0x00)); + + //SFPayloadCrc_Off + SX1276Write( REG_LR_MODEMCONFIG2,\ + ((uint8_t)((lora->sf + 6) << 4)) | 0x40); + + uint8_t temp = 0; + SX1276Read( 0x31,&temp); + if(0 == lora->sf) //SF = 6Ҫú + { + SX1276Write( 0x31,(temp& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); + } + else + { + SX1276Write( 0x31,(temp& 0xF8)|0x03); + SX1276Write( 0x37,0x0A); + } + + //ŻǷAutoAGCĬϿ +#if 0 + // ߼ + SX1276Write( REG_LR_MODEMCONFIG3,((TsXms>16.0)?\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON:RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF\ + )|RFLR_MODEMCONFIG3_AGCAUTO_ON); +#else + // SF12500kHz£뿪ʺܸ + SX1276Write( REG_LR_MODEMCONFIG3,(\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON\ + )|RFLR_MODEMCONFIG3_AGCAUTO_ON); +#endif + + return NORMAL; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : Ϊǣ preambleĻĬֵ +//////////////////////////////////////////////////////////////////////////////// +void SX1276_TxPacket(uint8_t*data,uint8_t size) +{ + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,8); + SX1276Write( REG_LR_PAYLOADLENGTH,size); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,data,size); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE_MASK)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : uint8_t clen ɱݰ´ֵЧ̶ݰΪֵ +// ز : +// ˵ : պpreambleûĬֵΪ +//////////////////////////////////////////////////////////////////////////////// +void Rx_mode(uint8_t clen) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,8); + SX1276Write( REG_LR_PAYLOADLENGTH,clen); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE_MASK | RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFտɱݰ +// : uint8_t*cbufָ,uint8_t *csizeسָ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxVariPacket(uint8_t*cbuf,uint8_t *csize) +{ + uint8_t reg; + + SX1276Read(REG_LR_IRQFLAGS, ®); + if(!(reg & RFLR_IRQFLAGS_RXDONE) || (reg & RFLR_IRQFLAGS_PAYLOADCRCERROR)) + *csize = 0; + else + { + SX1276Read(REG_LR_FIFORXCURRENTADDR, ®); + SX1276Read(REG_LR_NBRXBYTES,csize); + SX1276Write( REG_LR_FIFOADDRPTR,reg); + SX1276ReadFifo(cbuf,*csize); + } + SX1276Write(REG_LR_IRQFLAGS,0xff); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFչ̶ݰ +// : uint8_t*cbufָ,uint8_t csizeչ̶ +// ز : +// ˵ : 10kʱֻܲù̶ݰ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxFixiPacket(uint8_t*cbuf,uint8_t *csize) +{ + uint8_t reg; + + SX1276Read(REG_LR_IRQFLAGS, ®); + if(!(reg & RFLR_IRQFLAGS_RXDONE) || (reg & RFLR_IRQFLAGS_PAYLOADCRCERROR)) + *csize = 0; + else + { + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276ReadFifo(cbuf,*csize); + } + SX1276Write(REG_LR_IRQFLAGS,0xff); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFstandby״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_StandbyMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF벻ͬŵ +// : uint8_t ch Χ0-40 +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +uint8_t LSD_RF_FreqSet(uint8_t ch) +{ + uint8_t test_FRFMSB = 0,test_FRFMID=0,test_FRFLSB=0; +#if 0 + SX1276Write( REG_LR_FRFMSB,Freq_Cal_Tab[3*ch]); + SX1276Write( REG_LR_FRFMID,Freq_Cal_Tab[3*ch+1]); + SX1276Write( REG_LR_FRFLSB,Freq_Cal_Tab[3*ch+2]); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB !=Freq_Cal_Tab[3*ch]) + return 0; + if(test_FRFMID !=Freq_Cal_Tab[3*ch+1]) + return 0; + if(test_FRFLSB !=Freq_Cal_Tab[3*ch+2]) + return 0; +#else + const uint32_t FXOSC = 32000000ul; + float fstep = FXOSC / 524288.0; + uint32_t freq = 470000000ul + ch * 1000000ul; + uint32_t frf = (uint32_t) (freq / fstep + 0.5); + + LSD_RF_StandbyMode(); + SX1276Write( REG_LR_FRFMSB, (frf >> 16) & 0xFF); + SX1276Write( REG_LR_FRFMID, (frf >> 8) & 0xFF); + SX1276Write( REG_LR_FRFLSB, (frf & 0xff)); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB != ((frf >> 16) & 0xFF)) + return 0; + if(test_FRFMID != ((frf >> 8) & 0xFF)) + return 0; + if(test_FRFLSB != (frf & 0xff)) + return 0; +#endif + + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFù +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +uint8_t LSD_RF_PoutSet(uint8_t power) +{ + LSD_RF_StandbyMode(); + SX1276Write( REG_LR_PACONFIG, 0xf0|power); + uint8_t test = 0; + SX1276Read(REG_LR_PACONFIG,&test); + if((0xf0|power)!=test) + return 0; + SX1276Write( REG_LR_PADAC, 0x80|RFLR_PADAC_20DBM_ON ); + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : ݷɺDIO0ӵ͵ƽɸߵƽÿεô˺ԶȽDIO0Ϊͣȴߵƽ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SendPacket(uint8_t*cbuf,uint8_t csize) +{ + unsigned long int j=0xFFFFFF; //ʱãûҪʵ + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_L; //ֹDIO0ж + SX1276_TxPacket(cbuf,csize); // + while((!(DIO0_IFG&DIO0_BIT))&&j)j--; //ȴGDIO0ƽΪ + DIO0_IFG_L; //жϱ־λ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : uint8_t cclen ɱݰЧ̶ݰʱΪֵ +// ز : +// ˵ : ɺDIO0ӵ͵ƽɸߵƽ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RXmode(uint8_t cclen) +{ + Rx_mode(cclen); //RFջлRXģʽ + //SX_DIO0_DIR = 0; // + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_H; //ʹDIO0ж +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFSleep״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SleepMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + //P1OUT &= ~BIT4; //PA_TX ʼΪ0 + //P1OUT &= ~BIT5; //PA_TX ʼΪ0 Ŀǽʹ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF CADʼ +// : +// ز : +// ˵ : DIO1--CADDetected DIO3---CADDone +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_CADinit(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0xf0); + SX1276Write( REG_LR_PREAMBLELSB,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK,\ + ~(RFLR_IRQFLAGS_CADDONE|RFLR_IRQFLAGS_CADDETECTED)); + // + SX1276Write( REG_LR_DIOMAPPING1,\ + RFLR_DIOMAPPING1_DIO3_00 | RFLR_DIOMAPPING1_DIO1_10); + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write(REG_LR_IRQFLAGS,0xff); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFCADŵһ +// : +// ز : +// ˵ : ʱԼΪ(2^SF+32)/BW +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_CAD_Sample(void) +{ + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_CAD ); +} +//////////////////////////////////////////////////////////////////////////////// +// : WORʼ +// : +// ز : +// ˵ : DIO1 :ж DIO3CADʱжϣҲΪǽռжϣ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WORInit(void) +{ + LSD_RF_CADinit(); //CADܳʼ + //CADDoneʹ + //SX_DIO3_DIR=0; // + DIO3_IFG_L; //DIO3־λ + DIO3_IES_L; //DIO3شʽ + DIO3_IE_H; //DIO3ж + //CADDetectedʹ + //SX_DIO1_DIR=0; // + DIO1_IFG_L; //DIO1־λ + DIO1_IES_L; //DIO1شʽ + DIO1_IE_H; //ʹDIO1ж + //رDIO0жʹ + DIO0_IE_L; //ʹDIO0ж +} +//////////////////////////////////////////////////////////////////////////////// +// : ִWOR +// : uint8_t cclen 0˯ߡ1CADģʽ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WOR_Execute(uint8_t cclen) +{ + switch(cclen) + { + case 0: //˯ + LSD_RF_SleepMode(); //˯ģʽ + ON_Sleep_Timerout(); //˯߳ʱʱ + break; + case 1: //CADģʽ + OFF_Sleep_Timerout(); //ر˯߳ʱʱ + LSD_RF_CAD_Sample(); //CADһ + + break; + default: break; + } +} +//////////////////////////////////////////////////////////////////////////////// +// : WORRX +// : +// ز : +// ˵ : ˳WORRXģʽǰpreambleȻֵ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WOR_Exit(uint8_t cclen) +{ + OFF_Sleep_Timerout(); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PAYLOADLENGTH,cclen); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); + //SX_DIO0_DIR = 0; // + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_H; //ʹDIO0ж + + DIO1_IE_L; //ֹDIO1 + DIO3_IE_L; //ֹDIO3 + +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFͻѰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_Awake(uint8_t*cbuf,uint8_t csize) +{ + //SX_DIO0_DIR = 0; + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_L; //ֹDIO0ж + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PAYLOADLENGTH,csize); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,cbuf,csize); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_PREAMBLEMSB,0x03);//set preamble length + SX1276Write( REG_LR_PREAMBLELSB,0xEC);//set preamble length + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); + while((!DIO0_IFG)); //ȴGDIO0ƽΪ + + DIO0_IFG_L; //жϱ־λ + //껽ݰ󣬽ǰʱĻĬֵ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0);//set preamble length + SX1276Write( REG_LR_PREAMBLELSB,10);//set preamble length + +} + +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/20201020内部调通/FR2433-RFSX.h b/RF-AP/20201020内部调通/FR2433-RFSX.h new file mode 100644 index 0000000..37a798f --- /dev/null +++ b/RF-AP/20201020内部调通/FR2433-RFSX.h @@ -0,0 +1,307 @@ +#ifndef FR2433_RFSX +#define FR2433_RFSX +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: Haybin.Wu@studio +// ļ: +// 汾 V1.0 +// : IAR v6.20 +// : Haybin +// : 2016.05 +// : API for FR4133 +// ޸־ +//////////////////////////////////////////////////////////////////////////////// +#include +#include + +//====================================================================================== +#define CPU_MCLK 8000000 +#define DelayUs(us) __delay_cycles((CPU_MCLK/1000000UL) * us) +#define DelayMs(ms) __delay_cycles((CPU_MCLK/1000UL) * ms) +//////////////////////////////////////////////////////////////////////////////// +//ֻ޸ +//SX1276 SPI I/O definitions +#define SPI_PSEL P1SEL0 +#define SPI_PDIR P1DIR +#define SPI_POUT P1OUT +#define SPI_SI_BIT BIT2 +#define SPI_SO_BIT BIT3 +#define SPI_CLK_BIT BIT1 + +#define SPI_NSS_BIT BIT0 +#define SPI_NSS_PDIR P1DIR +#define SPI_NSS_POUT P1OUT + +//DIO0 +#define DIO0_BIT BIT6 +#define DIO0_DIR P1DIR +#define DIO0_IFG P1IFG +#define DIO0_IES P1IES +#define DIO0_IE P1IE + +//DIO1 +#define DIO1_BIT BIT7 +#define DIO1_DIR P1DIR +#define DIO1_IFG P1IFG +#define DIO1_IES P1IES +#define DIO1_IE P1IE +//DIO3 +#define DIO3_BIT BIT4 +#define DIO3_DIR P2DIR +#define DIO3_IFG P2IFG +#define DIO3_IES P2IES +#define DIO3_IE P2IE +//RST +#define RST_BIT BIT1 +#define RST_PDIR P3DIR +#define RST_POUT P3OUT + +//////////////////////////////////////////////////////////////////////////////// +//SX1276 SPI I/O definitions + +//NSS +#define SPI_NSS_DIR_OUT SPI_NSS_PDIR |= SPI_NSS_BIT //Ƭѡ out +#define SPI_NSS_OUT_1 SPI_NSS_POUT |= SPI_NSS_BIT //1 +#define SPI_NSS_OUT_0 SPI_NSS_POUT &= (~SPI_NSS_BIT) //1 + +//DIO0 +#define DIO0_IFG_H DIO0_IFG |= DIO0_BIT +#define DIO0_IFG_L DIO0_IFG &= ~DIO0_BIT +#define DIO0_IES_H DIO0_IES |= DIO0_BIT +#define DIO0_IES_L DIO0_IES &= ~DIO0_BIT +#define DIO0_IE_H DIO0_IE |= DIO0_BIT +#define DIO0_IE_L DIO0_IE &= ~DIO0_BIT + +//DIO1 +#define DIO1_IFG_H DIO1_IFG |= DIO1_BIT +#define DIO1_IFG_L DIO1_IFG &= ~DIO1_BIT +#define DIO1_IES_H DIO1_IES |= DIO1_BIT +#define DIO1_IES_L DIO1_IES &= ~DIO1_BIT +#define DIO1_IE_H DIO1_IE |= DIO0_BIT +#define DIO1_IE_L DIO1_IE &= ~DIO1_BIT + +//DIO3 +#define DIO3_IFG_H DIO3_IFG |= DIO3_BIT +#define DIO3_IFG_L DIO3_IFG &= ~DIO3_BIT +#define DIO3_IES_H DIO3_IES |= DIO3_BIT +#define DIO3_IES_L DIO3_IES &= ~DIO3_BIT +#define DIO3_IE_H DIO3_IE |= DIO3_BIT +#define DIO3_IE_L DIO3_IE &= ~DIO3_BIT + +//////////////////////////////////////////////////////////////////////////////// +// : SX1276 I/O pins definitions +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Init_IO( void ) +{ + //DIO0ΪP2.0 + //P2DIR &= ~BIT0; + //P2OUT |= BIT0; // Configure DIO0 as pulled-up + //P2REN |= BIT0; // DIO0pull-up register enable + DIO0_DIR&=~DIO0_BIT; + DIO0_IES_L; // DIO0 Hi/Low edge + DIO0_IE_L; // DIO0 interrupt enabled + DIO0_IFG_L; // DIO0IFG cleared + + //DIO1ΪP2.1 + //P2DIR &= ~BIT1; + //P2OUT |= BIT1; // Configure DIO1 as pulled-up + //P2REN |= BIT1; // DIO1pull-up register enable + DIO1_DIR&=~DIO1_BIT; + DIO1_IES_L; // DIO1 Hi/Low edge + DIO1_IE_L; // DIO1 interrupt enabled + DIO1_IFG_L; // DIO1IFG cleared + + //DIO3ΪP2.3 + //P2DIR &= ~BIT3; + //P2OUT |= BIT3; // Configure DIO3 as pulled-up + //P2REN |= BIT3; // DIO3pull-up register enable + DIO3_DIR&=~DIO3_BIT; + DIO3_IES_L; // DIO3 Hi/Low edge + DIO3_IE_L; // DIO3 interrupt enabled + DIO3_IFG_L; // DIO3IFG cleared + + + //SX1276 SPI I/O definitions + // Configure SPI + //SPI SET + SPI_NSS_DIR_OUT; + SPI_NSS_OUT_1; // /CS disable + + // SPI option select + SPI_PSEL |= SPI_SI_BIT+SPI_SO_BIT+SPI_CLK_BIT; + + UCB0CTLW0 |= UCSWRST; // **Put state machine in reset** + UCB0CTLW0 |= UCMST|UCSYNC|UCCKPH|UCMSB; // 3-pin, 8-bit SPI master + // Clock polarity high, MSB + UCB0CTLW0 |= UCSSEL__SMCLK; // SMCLK + UCB0BR0 = 1; // /2,fBitClock = fBRCLK/(UCBRx+1). + UCB0BR1 = 0; // + UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** + + //SX1276 RESET I/O definitions + RST_PDIR |= RST_BIT; + RST_POUT |= RST_BIT; + +} + +//////////////////////////////////////////////////////////////////////////////// +// : ˯߳ʱʱ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void ON_Sleep_Timerout(void) +{ + + //Timer1_A3 setup + TA1R =0; //ʱ + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768; + TA0CTL |= TASSEL_1 | MC_1; //ʱʱ +} +//////////////////////////////////////////////////////////////////////////////// +// : ر˯߳ʱʱ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void OFF_Sleep_Timerout(void) +{ + //TA0R =0; //ʱ + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768; + TA0CTL = TASSEL_1 | MC_0; //رնʱ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF λ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Reset(void) +{ + RST_POUT &= ~RST_BIT; //ӲλIO0 + DelayMs(6); //ʱ + RST_POUT |= RST_BIT; //Ϊ1 + DelayMs(5); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ +// : uint8_t addr,Ĵַ uint8_t *buffer,ָ uint8_t sizeָ볤 +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +{ + uint8_t i; + SPI_PSEL |= SPI_SO_BIT;//SPIbugĹ쳣 + SPI_NSS_OUT_0; +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + UCB0IFG &= ~UCRXIFG; // Clear flag + UCB0TXBUF = (addr | 0x80); // Send address + while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish + UCB0IFG &= ~UCTXIFG; // Clear flag + for( i = 0; i < size; i++ ) + { + UCB0TXBUF = buffer[i]; // Send data + while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish + UCB0IFG &= ~UCTXIFG; + } +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + SPI_NSS_OUT_1; + SPI_PSEL &= ~SPI_SO_BIT;//SPIbugĹ쳣 +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ +// : uint8_t addr,Ĵַ uint8_t *buffer,洢ָ uint8_t sizeҪij +// ز : ݷص*buffer +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +{ + uint8_t i; + SPI_PSEL |= SPI_SO_BIT;//SPIbugĹ쳣 + SPI_NSS_OUT_0; +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + UCB0IFG &= ~UCRXIFG; // Clear flag + UCB0TXBUF = (addr & 0x7F); // Send address + while (!(UCB0IFG&UCTXIFG)); // Wait for end of addr byte TX + UCB0IFG &= ~UCTXIFG; // Clear flag + for( i = 0; i < size; i++ ) + { + UCB0TXBUF = 0; //Initiate next data RX + while (!(UCB0IFG&UCRXIFG)); // Wait for RX to finish + buffer[i] = UCB0RXBUF; // Store data from last data RX + //ȡUCB0RXBUFIFGԶReset + } +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + SPI_NSS_OUT_1; + SPI_PSEL &= ~SPI_SO_BIT;//SPIbugĹ쳣 + UCB0IFG=0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַд1ֽ +// : uint8_t addr,Ĵַ uint8_t data +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Write( uint8_t addr, uint8_t data ) +{ + SX1276WriteBuffer( addr, &data, 1 ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ1ֽ +// : uint8_t addr,Ĵַ uint8_t *dataݴ洢ַ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Read( uint8_t addr, uint8_t *data ) +{ + SX1276ReadBuffer( addr, data, 1 ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF FIFOд +// : uint8_t *buffer,ָ uint8_t size +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteFifo( uint8_t *buffer, uint8_t size ) +{ + SX1276WriteBuffer( 0, buffer, size ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF FIFO +// : uint8_t *buffer,ָ uint8_t size +// ز : uint8_t *buffer 洢ȡ +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276ReadFifo( uint8_t *buffer, uint8_t size ) +{ + SX1276ReadBuffer( 0, buffer, size ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF TX/RXPAл +// : bool txEnable л߼ +// ز : +// ˵ :棺ΪTX٣ΪRX ΪӲPAIO +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteRxTx( bool txEnable ) +{ + if( txEnable != 0 ) //Ϊ棬ΪTX + { + ; + } + else //Ϊ٣ΪRX + { + ; + } +} + +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/20201020内部调通/RF-Module.c b/RF-AP/20201020内部调通/RF-Module.c new file mode 100644 index 0000000..2823370 --- /dev/null +++ b/RF-AP/20201020内部调通/RF-Module.c @@ -0,0 +1,491 @@ +// Haybin_Wu +// Shenitech-RD +// 2016.5 +// Built with IAR Embedded Workbench v6.2 +//****************************************************************************** +// Modify by Qian Xianghong +// 2020.10 +// ޸־ģɴںRF˫͸ģʽ +//****************************************************************************** +#include +#include +#include +#include +#include "FR2433-RFSX.h" +#include "RF_SX1276.h" + +// Ƶò +lora_param_t Lora_Param; + +#define TRAN_BUF_SIZE (1024) + +// UA1ӡ +char printBuf[200]; +void uart_print() +{ +#if 0 // ӡڵ2MD0MD1ģʽѡ + char *p = printBuf; + while(*p) + { + if(*p == '\n') // ǰӻس + { + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = '\r'; + } + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = *p++; + } +#endif +} + +// ɱĺ궨 +#define PRINTF(format, ...) \ +{ \ + snprintf(printBuf, sizeof(printBuf), format, ##__VA_ARGS__); \ + uart_print(); \ +} + +// UA0λݵbuf +uint8_t UA0_RxBuf[TRAN_BUF_SIZE] = {0}; +uint16_t UA0_RxBuf_Length = 0; +uint16_t UA0_RxBuf_offset = 0; +// UA0ճʱ +volatile uint8_t UA0_Rx_Timeout = 1; + +// RFݵbuf +uint8_t RF_RxBuf[TRAN_BUF_SIZE] = {0}; +uint16_t RF_RxBuf_Length = 0; +uint16_t RF_RxBuf_offset = 0; +// RFճʱ־ +volatile uint8_t RF_Rx_Timeout = 1; + +//////////////////////////////////////////////////////////////////////////////// +// ڳʼ +void UA0_Init(uint32_t baudrate) +{ + // Configure UART + UCA0CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + if(baudrate == 115200) + { + UCA0BR0 = 4; // 8000000/16/115200//λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.44444 + UCA0MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢Baud Rate + } + else if(baudrate == 38400) + { + UCA0BR0 = 13; // 8000000/16/38400 /λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.33333 + UCA0MCTLW = 0x8400 | UCOS16 | UCBRF_0;//΢Baud Rate + } + else + { + UCA0BR0 = 52; // 8000000/16/9600 /λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.33333 + UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1;//΢Baud Rate + } + UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt +} + +// Ӧ +void UA0_Response(char *s) +{ + while(*s) + { + while(!(UCA0IFG & UCTXIFG)); + UCA0TXBUF = *s++; + } + // ȴͽ + while(!(UCA0IFG & UCTXCPTIFG)); + DelayMs(2); +} + +//////////////////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////////////////// + int main(void) +{ + uint8_t sendCh; + + WDTCTL = (WDTPW | WDTHOLD); // Stop WDT + // Port Configuration all un-used pins to output low + P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; + P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; + PM5CTL0 &= ~LOCKLPM5;//Ź + + // Configure DCO Clock + //ⲿʱԴ + P2SEL0 |= (BIT0 | BIT1); // set XT1 pin as second function + do + { + CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag + SFRIFG1 &= ~OFIFG; + } while (SFRIFG1 & OFIFG); // Test oscillator fault flag + //־ڽ͹ + + __bis_SR_register(SCG0); // disable FLL + CSCTL3 |= SELREF__XT1CLK; // ⲿ 32768hz reference source + CSCTL0 = 0; // clear DCO and MOD registers + CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first + CSCTL1 |= DCORSEL_3; //DCO=8Mhz + CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz + __delay_cycles(3); + __bic_SR_register(SCG0); // enable FLL + while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked + + CSCTL4 = SELREF__XT1CLK + SELMS__DCOCLKDIV;// set XT1CLK(32768Hz) as ACLK source & MCLK/SMCLK=DCO + + //Timer0_A0 setup + TA0CCTL0 = CCIE; // TACCR0 interrupt enabled + TA0CCR0 = 32768 / 32; // ڽճʱ: 1000/32=31.25ms + TA0CTL = MC__STOP | TACLR; // Stop mode, Clear counter + + //Timer1_A0 setup + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768 / 4; // RFճʱ: 1000/4=250ms + TA1CTL = MC__STOP | TACLR; // Stop mode, Clear counter + + // ģȱʡ + Lora_Param.sof = 0xC2; + Lora_Param.addr = 0xADF2; // ͨŵַ0xADF2 + Lora_Param.sf = 6; // sf=12 + Lora_Param.baud = 3; // 9600 + Lora_Param.cr = 0; // cr=4/5 + Lora_Param.ch = 9; // 479MHz + Lora_Param.power = 1; // 17dBm + Lora_Param.freqcast = 0; // freqcast off + Lora_Param.bw = 9; // 500kHz + Lora_Param.unicast = 0; // unicast off + + // Configure UART pins + P1SEL1 &= ~(BIT4 | BIT5); // set 2-UART pin as second function + P1SEL0 |= (BIT4 | BIT5); // set 2-UART pin as second function + if(Lora_Param.baud == 7) + UA0_Init(115200); + else if(Lora_Param.baud == 5) + UA0_Init(38400); + else + UA0_Init(9600); + +#if 0 // ôӡ + // Configure UART pins + P2SEL1 &= ~(BIT5 | BIT6); // set 2-UART pin as second function + P2SEL0 |= (BIT5 | BIT6); // set 2-UART pin as second function + // Configure UART + UCA1CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + UCA1BR0 = 4; // 8000000/16/115200//λ16 UCOS16λҪλ + UCA1BR1 = 0; // Fractional portion = 0.44444 + UCA1MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢Baud Rate + UCA1CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt + + // ӡλԭ(Դ𣬲Ź) + PRINTF("\nModule reseted: %04X\n", PMMIFG); + +#else // MD0MD1ģʽ + P2SEL1 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO + P2SEL0 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO + P2DIR &= ~(BIT5 | BIT6); // Input + P2REN |= (BIT5 | BIT6); // enable pull + P2OUT &= ~(BIT5 | BIT6); // pull-down + + P2DIR |= BIT3; // Output + P2OUT |= BIT3; // Output high +#endif + + _EINT(); + +#if 0 + // ӡλԭ(Դ𣬲Ź) + RF_RxBuf[0] = PMMIFG >> 8; + RF_RxBuf[1] = PMMIFG & 0xFF; + RF_RxBuf_Length = 2; + RF_RxBuf_offset = 0; + UCA0IE |= UCTXIE; + while(UCA0IE & UCTXIE); +#endif + // Ĵλԭ + SYSRSTIV; + + //ģʼ + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + // ʼڽģʽ + LSD_RF_RXmode(RF_PAYLOAD_LEN); + // ĬϷŵ + sendCh = Lora_Param.ch; + + // Ź: ʱʱΪ2^27/SMCLK8000000ƵԼΪ16s + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + while(1) + { +#if 1 + // TODO: ι + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + // ģʽ + if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6)) + { + if(UA0_RxBuf_Length - UA0_RxBuf_offset >= sizeof(Lora_Param)) + { + if(UA0_RxBuf[UA0_RxBuf_offset] == 0xC2) + { + // + memmove(&Lora_Param, UA0_RxBuf + UA0_RxBuf_offset, sizeof(Lora_Param)); + // ߵַߵֽ + Lora_Param.addr = (Lora_Param.addr << 8) | (Lora_Param.addr >> 8); + + //ģʼ + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + // б仯ģʼ + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + // Ĭϴڽģʽ + LSD_RF_RXmode(RF_PAYLOAD_LEN); + // ĬϷŵ + sendCh = Lora_Param.ch; + // Ӧ + UA0_Response("OK\r\n"); + + // ı䴮ڲ + if(Lora_Param.baud == 7) + UA0_Init(115200); + else if(Lora_Param.baud == 5) + UA0_Init(38400); + else + UA0_Init(9600); + } + + UA0_RxBuf_offset = UA0_RxBuf_Length; + } + } + // ͸ģʽ + else if((P2IN & (BIT5 | BIT6)) == 0) +#endif + { + if(UA0_RxBuf_Length > UA0_RxBuf_offset) + { + // 㴫䣬ָĿַŵ + if(Lora_Param.unicast) // 㷢 + { + if(UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 3) + sendCh = UA0_RxBuf[2]; + } + else if(Lora_Param.freqcast) // ָŵ + { + if(UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 1) + { + sendCh = UA0_RxBuf[0]; + UA0_RxBuf_offset = 1; // ͵1ֽ + } + } + + if(UA0_RxBuf_Length - UA0_RxBuf_offset >= RF_PAYLOAD_LEN) + { + LSD_RF_FreqSet(sendCh); + LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, RF_PAYLOAD_LEN); + UA0_RxBuf_offset += RF_PAYLOAD_LEN; + PRINTF("Send packet\n"); + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + + } + else if(UA0_Rx_Timeout) + { + LSD_RF_FreqSet(sendCh); + LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, UA0_RxBuf_Length - UA0_RxBuf_offset); + UA0_RxBuf_offset = UA0_RxBuf_Length; + PRINTF("Send packet\n"); + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + } + } + } + + if(UA0_Rx_Timeout && UA0_RxBuf_offset == UA0_RxBuf_Length) + P2OUT |= BIT3; // Output high + } +} + +// Port 1 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=PORT1_VECTOR +__interrupt void Port_1(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(PORT1_VECTOR))) Port_1 (void) +#else +#error Compiler not supported! +#endif +{ + uint8_t offset = 0; + uint8_t len[1] = {0}; + uint8_t buf[RF_PAYLOAD_LEN]; + if(DIO0_IFG&DIO0_BIT) //ݴжϴ + { + // ж + DIO0_IFG &= ~DIO0_BIT; + + // ȡRF + LSD_RF_RxVariPacket(buf, len); //տɱݰΪʣֻýչ̶ݰ + + if(len[0] == 0) + return; + + TA1CTL = MC__STOP | TACLR; // ֹͣʱλ + TA1CTL = TASSEL__ACLK | MC__UP; // ¿ʼʱ + + offset = 0; + if(RF_Rx_Timeout) // µһݵ + { + RF_Rx_Timeout = 0; + + // λ + RF_RxBuf_Length = 0; + RF_RxBuf_offset = 0; + + if(Lora_Param.unicast) + { + // 㴫䣬ַŵУʧ + if(len[0] <= 3 || buf[2] != Lora_Param.ch || ((buf[0] << 8) | buf[1]) != Lora_Param.addr) + return; + // ǰ3ַ + offset = 3; + len[0] -= offset; + } + } + + PRINTF("Recv packet\n"); + + // ͸ģʽ + if((P2IN & (BIT5 | BIT6)) == 0) + { + if(RF_RxBuf_Length + len[0] <= TRAN_BUF_SIZE) + { + memmove(RF_RxBuf + RF_RxBuf_Length, buf + offset, len[0]); + // жϷʽ򴮿ת + RF_RxBuf_Length += len[0]; + UCA0IE |= UCTXIE; + } + } + } +} + +// Timer0 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER0_A0_VECTOR +__interrupt void Timer0_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) Timer0_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ֹͣʱλ + TA0CTL = MC__STOP | TACLR; + // ڽճʱ + UA0_Rx_Timeout = 1; +} + +// Timer1 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER1_A0_VECTOR +__interrupt void Timer1_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER1_A0_VECTOR))) Timer1_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ֹͣʱλ + TA1CTL = MC__STOP | TACLR; + // RFճʱ + RF_Rx_Timeout = 1; +} + +// UAR0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=USCI_A0_VECTOR +__interrupt void USCI_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ж + if((UCA0IE & UCRXIE) && (UCA0IFG & UCRXIFG)) + { + uint8_t c = UCA0RXBUF; + + TA0CTL = MC__STOP | TACLR; // ֹͣʱλ + TA0CTL = TASSEL__ACLK | MC__UP; // ¿ʼʱ + + if(UA0_Rx_Timeout) // µһݵ + { + UA0_Rx_Timeout = 0; + // λ + UA0_RxBuf_Length = 0; + UA0_RxBuf_offset = 0; + } + + if(UA0_RxBuf_Length < TRAN_BUF_SIZE) + { +#if 1 + // ģʽ + if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6)) + { + // 1ַΪ0xC2 + if(UA0_RxBuf_Length > 0 || c == 0xC2) + UA0_RxBuf[UA0_RxBuf_Length++] = c; + } + // ͸ģʽ + else if((P2IN & (BIT5 | BIT6)) == 0) +#endif + { + // ͸ + UA0_RxBuf[UA0_RxBuf_Length++] = c; + } + + P2OUT &= ~BIT3; // Output low + } + } + + // ж + if((UCA0IE & UCTXIE) && (UCA0IFG & UCTXIFG)) + { + UCA0TXBUF = RF_RxBuf[RF_RxBuf_offset++]; // ַ + if(RF_RxBuf_offset >= RF_RxBuf_Length) // ȫ + { + // ֹж + UCA0IE &= ~UCTXIE; + } + } +} diff --git a/RF-AP/20201020内部调通/RF_SX1276.h b/RF-AP/20201020内部调通/RF_SX1276.h new file mode 100644 index 0000000..9869a81 --- /dev/null +++ b/RF-AP/20201020内部调通/RF_SX1276.h @@ -0,0 +1,1295 @@ +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: Haybin.Wu@studio +// ļ: +// 汾 V1.0 +// : IAR v6.20 +// : Haybin +// : 2016.05 +// : API +// ޸־ +//////////////////////////////////////////////////////////////////////////////// +// Modify by Qian Xianghong +// 2020.10 +// ޸־ +// 1. LSD_RF_SendPacket(): +// ޸жDIO0־ȷɣúʱ +// ǰ볤޸Ϊ8.Ĭֵмһ£ +// 2. LSD_RF_RXmode(): +// PayloadCrcErrorʶ +// ǰ볤޸Ϊ8.Ĭֵмһ£ +// 3. LSD_RF_RxVariPacket(): +// жRxDonePayloadCRCErrorʶ +// ȶȡREG_LR_FIFORXCURRENTADDRĴֵٴӸõַʼȡݡ +// 4. LSD_RF_RxFixiPacket(): +// жRxDonePayloadCRCErrorʶ +// 5. SX127x_initLora()ڸسʼLoRa +//////////////////////////////////////////////////////////////////////////////// +#include +#include +#include "FR2433-RFSX.h" +#ifndef RF_SX1276 +#define RF_SX1276 + +uint8_t LSD_RF_FreqSet(uint8_t ch); +uint8_t LSD_RF_PoutSet(uint8_t power); +//====================================================================================== +#define RF_PAYLOAD_LEN (64) + +#pragma pack(push, 1) +// LORAҫ +typedef struct +{ + uint8_t sof; // ǰ룬̶Ϊ0xC2 + uint16_t addr; // ͨŵַ + unsigned char sf : 3; // Ƶ: 0-1-7,...,6-12,7- + unsigned char baud : 3; // ڲʣ3-9600,7-115200, ౣ + unsigned char cr : 2; // : 0-4/5,1-4/6,2-4/7,3-4/8 + uint8_t ch; // ͨŵ: 0~40(470M~510M),ౣ + unsigned char power : 2; // Power: 0-20dBm,1-17dBm,2-14dBm,3-11dBm + unsigned char freqcast: 1; // Ƿָŵ + unsigned char bw : 4; // 0-7.8kHz,1-10.4kHz,...,9-500kHz, ౣ + unsigned char unicast : 1; // Ƿ񶨵㷢 +} lora_param_t; +#pragma pack(pop) +//====================================================================================== +/*! + * SX1276 LoRa General parameters definition + */ +typedef struct sLoRaSettings +{ + uint32_t RFFrequency; + int8_t Power; + uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz, + // 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved] + uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips] + uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + bool CrcOn; // [0: OFF, 1: ON] + bool ImplicitHeaderOn; // [0: OFF, 1: ON] + bool RxSingleOn; // [0: Continuous, 1 Single] + bool FreqHopOn; // [0: OFF, 1: ON] + uint8_t HopPeriod; // Hops every frequency hopping period symbols + uint32_t TxPacketTimeout; + uint32_t RxPacketTimeout; + uint8_t PayloadLength; +}tLoRaSettings; + +/*! + * RF packet definition + */ +#define RF_BUFFER_SIZE_MAX 128 +#define RF_BUFFER_SIZE 80 + +/*! + * RF state machine + */ +//LoRa +typedef enum +{ + RFLR_STATE_IDLE, + RFLR_STATE_RX_INIT, + RFLR_STATE_RX_RUNNING, + RFLR_STATE_RX_DONE, + RFLR_STATE_RX_TIMEOUT, + RFLR_STATE_TX_INIT, + RFLR_STATE_TX_RUNNING, + RFLR_STATE_TX_DONE, + RFLR_STATE_TX_TIMEOUT, + RFLR_STATE_CAD_INIT, + RFLR_STATE_CAD_RUNNING, +}tRFLRStates; + +/*! + * SX1276 definitions + */ +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +/*! + * SX1276 Internal registers Address + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +//#define REG_LR_BANDSETTING 0x04 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_NBRXBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 + +/*! + * SX1276 LoRa bit control definition + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegBandSetting + */ +#define RFLR_BANDSETTING_MASK 0x3F +#define RFLR_BANDSETTING_AUTO 0x00 // Default +#define RFLR_BANDSETTING_DIV_BY_1 0x40 +#define RFLR_BANDSETTING_DIV_BY_2 0x80 +#define RFLR_BANDSETTING_DIV_BY_6 0xC0 + + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RFLR_LNA_BOOST_LF_GAIN 0x08 +#define RFLR_LNA_BOOST_LF_IP3 0x10 +#define RFLR_LNA_BOOST_LF_BOOST 0x18 +#define RFLR_LNA_RXBANDFORCE_MASK 0xFB +#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + + + +/*! + * RegFifoRxNbBytes (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueMsb (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueLsb (Read Only) // + */ + + +/*! + * RegRxPacketCntValueMsb (Read Only) // + */ + + + /*! + * RegRxPacketCntValueLsb (Read Only) // + */ + + + /*! + * RegModemStat (Read Only) // + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) // + */ + + + /*! + * RegPktRssiValue (Read Only) // + */ + + +/*! + * RegRssiValue (Read Only) // + */ + + + /*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F + +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + + /*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + + +/*! + * RegHopChannel (Read Only) + */ + +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40 +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegModemConfig3 + */ +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +/*! + * RegFormerTemp + */ + +typedef struct sSX1276LR +{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + + uint8_t RegTestReserved02[0x06 - 0x02]; // 0x02-0x05 + // uint8_t RegRes02; // 0x02 + // uint8_t RegRes03; // 0x03 + // uint8_t RegBandSetting; // 0x04 + // uint8_t RegRes05; // 0x05 + + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + // LoRa registers + uint8_t RegFifoAddrPtr; // 0x0D + uint8_t RegFifoTxBaseAddr; // 0x0E + uint8_t RegFifoRxBaseAddr; // 0x0F + uint8_t RegFifoRxCurrentAddr; // 0x10 + uint8_t RegIrqFlagsMask; // 0x11 + uint8_t RegIrqFlags; // 0x12 + uint8_t RegNbRxBytes; // 0x13 + uint8_t RegRxHeaderCntValueMsb; // 0x14 + uint8_t RegRxHeaderCntValueLsb; // 0x15 + uint8_t RegRxPacketCntValueMsb; // 0x16 + uint8_t RegRxPacketCntValueLsb; // 0x17 + uint8_t RegModemStat; // 0x18 + uint8_t RegPktSnrValue; // 0x19 + uint8_t RegPktRssiValue; // 0x1A + uint8_t RegRssiValue; // 0x1B + uint8_t RegHopChannel; // 0x1C + uint8_t RegModemConfig1; // 0x1D + uint8_t RegModemConfig2; // 0x1E + uint8_t RegSymbTimeoutLsb; // 0x1F + uint8_t RegPreambleMsb; // 0x20 + uint8_t RegPreambleLsb; // 0x21 + uint8_t RegPayloadLength; // 0x22 + uint8_t RegMaxPayloadLength; // 0x23 + uint8_t RegHopPeriod; // 0x24 + uint8_t RegFifoRxByteAddr; // 0x25 + uint8_t RegModemConfig3; // 0x26 + uint8_t RegTestReserved27[0x31 - 0x27]; // 0x27-0x30 + //void SX1276LoRaSetNbTrigPeaks( uint8_t value )õ + uint8_t RegTestReserved31; // 0x31 + uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x3F + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + + uint8_t RegTestReserved43[0x4B - 0x43]; // 0x43-0x4A + uint8_t RegTcxo; // 0x4B + uint8_t RegTestReserved4C; // 0x4C + uint8_t RegPaDac; // 0x4D + uint8_t RegTestReserved4E[0x5B - 0x4E]; // 0x4E-0x5A + uint8_t RegFormerTemp; // 0x5B + uint8_t RegTestReserved5C[0x61 - 0x5C]; // 0x5C-0x60 + // Additional settings + uint8_t RegAgcRef; // 0x61 + uint8_t RegAgcThresh1; // 0x62 + uint8_t RegAgcThresh2; // 0x63 + uint8_t RegAgcThresh3; // 0x64 + uint8_t RegTestReserved65[0x70 - 0x65]; // 0x65-0x6F + uint8_t RegPll; // 0x70 +}tSX1276LR; +////////////////////////////////////////////////////////////////////////////// +typedef enum +{ + Init_LoRa_0_8K, + Init_LoRa_4_8K, + Init_LoRa_10k, +}tSX127xInitPara; //ö + +typedef enum +{ + NORMAL, // + PARAMETER_INVALID, // + SPI_READCHECK_WRONG, //SPI +}tSX127xError; //ö + +typedef enum +{ + SLEEP, + STANDBY, + TX_ONGOING, + RX_ONGOING, +}tSX127xState; //RF״̬ûԲʹ + +typedef enum +{ + HOLDON, + TX, + LISTENING, +}tRadio_Machine; //߼״̬ûԲʹ + +typedef enum +{ + MASTER, + SLAVE, +}tMasterSlave; //ö ʱ + +typedef struct +{ + tMasterSlave MasterSlave; // + tSX127xState SX127xState; //״̬ + tRadio_Machine Machine; //߼״̬ +}stRadio_Situation; //״̬ṹ + +const unsigned char Freq_Cal_Tab[]= +{ + 0x75,0x80,0x00,//470MHz + 0x75,0xC0,0x00,//471MHz + 0x76,0x00,0x00,//472MHz + 0x76,0x40,0x00,//473MHz + 0x76,0x80,0x00,//474MHz + 0x76,0xC0,0x00,//475MHz + 0x77,0x00,0x00,//476MHz + 0x77,0x40,0x00,//477MHz + 0x77,0x80,0x00,//478MHz + 0x77,0xC0,0x00,//479MHz + 0x78,0x00,0x00,//480MHz + 0x78,0x40,0x00,//481MHz + 0x78,0x80,0x00,//482MHz + 0x78,0xC0,0x00,//483MHz + 0x79,0x00,0x00,//484MHz + 0x79,0x40,0x00,//485MHz + 0x79,0x80,0x00,//486MHz + 0x79,0xC0,0x00,//487MHz + 0x7A,0x00,0x00,//488MHz + 0x7A,0x40,0x00,//489MHz + 0x7A,0x80,0x00,//490MHz + 0x7A,0xC0,0x00,//491MHz + 0x7B,0x00,0x00,//492MHz + 0x7B,0x40,0x00,//493MHz + 0x7B,0x80,0x00,//494MHz + 0x7B,0xC0,0x00,//495MHz + 0x7C,0x00,0x00,//496MHz + 0x7C,0x40,0x00,//497MHz + 0x7C,0x80,0x00,//498MHz + 0x7C,0xC0,0x00,//499MHz + 0x7D,0x00,0x00,//500MHz + 0x7D,0x40,0x00,//501MHz + 0x7D,0x80,0x00,//502MHz + 0x7D,0xC0,0x00,//503MHz + 0x7E,0x00,0x00,//504MHz + 0x7E,0x40,0x00,//505MHz + 0x7E,0x80,0x00,//506MHz + 0x7E,0xC0,0x00,//507MHz + 0x7F,0x00,0x00,//508MHz + 0x7F,0x40,0x00,//509MHz + 0x7F,0x80,0x00,//510MHz +}; + +//extern stRadio_Situation SX127xSituation; +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : tSX127xInitPara initPara Init_LoRa_0_8K, Init_LoRa_4_8K , Init_LoRa_10k, +// ز : tSX127xError ö +// ˵ : ʼʱŵʼĬΪ0ŵ +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_init(tSX127xInitPara initPara) +{ + uint8_t test = 0; + if(initPara>Init_LoRa_10k) // + { + return PARAMETER_INVALID; // + } + SX1276Init_IO(); // PAIOڳʼ + SX1276Reset(); //λRF + //init Regs + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PACONFIG, 0xff ); + SX1276Write( REG_LR_PADAC, RFLR_PADAC_20DBM_ON ); + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US); + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA); + SX1276Write( REG_LR_PAYLOADLENGTH,2); + SX1276Write( REG_LR_MODEMCONFIG3,\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON| + RFLR_MODEMCONFIG3_AGCAUTO_ON); + //BW,SF,CR,Header,CRC +// SX1276Write( REG_LR_MODEMCONFIG2,0xFF); +// SX1276Write( REG_LR_SYMBTIMEOUTLSB,0xFF); + switch(initPara){ + case Init_LoRa_0_8K: +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON| +// RFLR_MODEMCONFIG3_AGCAUTO_ON); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_125_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_9|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); + SX1276Write( REG_LR_PREAMBLELSB,10); + SX1276Write(0x31,0x55); + SX1276Read( 0x31,&test); + break; + case Init_LoRa_4_8K: +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF| +// RFLR_MODEMCONFIG3_AGCAUTO_OFF); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_8|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); +// SX1276Write( REG_LR_PREAMBLEMSB,1); + SX1276Write( REG_LR_PREAMBLELSB,10); + break; + case Init_LoRa_10k: + SX1276Read( 0x31,&test); + SX1276Write( 0x31,(test& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF| +// RFLR_MODEMCONFIG3_AGCAUTO_ON); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_ON); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_6|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); +// SX1276Write( REG_LR_PREAMBLEMSB,4); + SX1276Write( REG_LR_PREAMBLELSB,10); + break; + default: + break; + } + if(!LSD_RF_FreqSet(1)) //Ϊ0ŵ + return SPI_READCHECK_WRONG; + + return NORMAL; +} + +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : lora_param_t lora +// ز : tSX127xError ö +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_initLora(lora_param_t *lora) +{ + static uint8_t first = 1; + + // + if(lora->sof != 0xC2 || lora->sf > 6 || (lora->baud != 3 && lora->baud != 5 && lora->baud != 7) || lora->ch > 40 || lora->bw > 9) + return PARAMETER_INVALID; + + if(first) + { + first = 0; + SX1276Init_IO(); // PAIOڳʼ + } + SX1276Reset(); //λRF + + //лLoRamodestandby״̬ + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + + /*------------------------------------------------ + SPI ֤ */ + uint8_t test = 0; + SX1276Write( REG_LR_HOPPERIOD,0x91 );//ѡһòļĴ֤ + SX1276Read( REG_LR_HOPPERIOD,&test); + if(test!=0x91) + return SPI_READCHECK_WRONG; + + SX1276Write( REG_LR_PACONFIG, 0xff ); + + //Frequency Configuration + LSD_RF_FreqSet(lora->ch); //Ƶ + //PA Configuration + switch(lora->power) + { + case 0: // 20dBm + LSD_RF_PoutSet(15); + break; + case 1: // 17dBm + LSD_RF_PoutSet(15); + break; + case 2: // 14dBm + LSD_RF_PoutSet(12); + break; + case 3: // 11dBm + LSD_RF_PoutSet(9); + break; + } + + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US); + // PA Rampʱ䣬ûLDOܿʵPA Rampʱ + // Rampʱ̳LDOʱֽTXϵͳΪRFźŲֵ + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);//ر Over Current Protection + + //PayloadLength ʼ + SX1276Write( REG_LR_PAYLOADLENGTH, RF_PAYLOAD_LEN); + //ע⣬ͷģʽImplicit Headerʱǰ涨շ˫PL + + //BWCRImplictHeader_On (SF6) / Off (SF7~12) + SX1276Write( REG_LR_MODEMCONFIG1,\ + (((uint8_t)(lora->bw << 4)) | ((uint8_t) ((lora->cr + 1) << 1))) | (lora->sf == 0 ? 0x01 : 0x00)); + + //SFPayloadCrc_Off + SX1276Write( REG_LR_MODEMCONFIG2,\ + ((uint8_t)((lora->sf + 6) << 4)) | 0x40); + + uint8_t temp = 0; + SX1276Read( 0x31,&temp); + if(0 == lora->sf) //SF = 6Ҫú + { + SX1276Write( 0x31,(temp& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); + } + else + { + SX1276Write( 0x31,(temp& 0xF8)|0x03); + SX1276Write( 0x37,0x0A); + } + + //ŻǷAutoAGCĬϿ + // SF12500kHz£뿪ʺܸ + SX1276Write( REG_LR_MODEMCONFIG3,(\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON\ + )|RFLR_MODEMCONFIG3_AGCAUTO_ON); + + // Ƶѡ + SX1276Write( REG_LR_DIOMAPPING2, RFLR_DIOMAPPING2_DIO4_01); + + return NORMAL; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : Ϊǣ preambleĻĬֵ +//////////////////////////////////////////////////////////////////////////////// +void SX1276_TxPacket(uint8_t*data,uint8_t size) +{ + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,8); + SX1276Write( REG_LR_PAYLOADLENGTH,size); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,data,size); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE_MASK)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : uint8_t clen ɱݰ´ֵЧ̶ݰΪֵ +// ز : +// ˵ : պpreambleûĬֵΪ +//////////////////////////////////////////////////////////////////////////////// +void Rx_mode(uint8_t clen) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,8); + SX1276Write( REG_LR_PAYLOADLENGTH,clen); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE_MASK | RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFտɱݰ +// : uint8_t*cbufָ,uint8_t *csizeسָ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxVariPacket(uint8_t*cbuf,uint8_t *csize) +{ + uint8_t flag, ptr; + + SX1276Read(REG_LR_IRQFLAGS, &flag); + + SX1276Read(REG_LR_FIFORXCURRENTADDR, &ptr); + SX1276Read(REG_LR_NBRXBYTES,csize); + SX1276Write( REG_LR_FIFOADDRPTR,ptr); + SX1276ReadFifo(cbuf,*csize); + SX1276Write(REG_LR_IRQFLAGS,0xff); + + if(!(flag & RFLR_IRQFLAGS_RXDONE) || (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR)) + *csize = 0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RFչ̶ݰ +// : uint8_t*cbufָ,uint8_t csizeչ̶ +// ز : +// ˵ : 10kʱֻܲù̶ݰ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxFixiPacket(uint8_t*cbuf,uint8_t *csize) +{ + uint8_t flag; + + SX1276Read(REG_LR_IRQFLAGS, &flag); + + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276ReadFifo(cbuf,*csize); + SX1276Write(REG_LR_IRQFLAGS,0xff); + + if(!(flag & RFLR_IRQFLAGS_RXDONE) || (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR)) + *csize = 0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RFstandby״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_StandbyMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF벻ͬŵ +// : uint8_t ch Χ0-40 +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +uint8_t LSD_RF_FreqSet(uint8_t ch) +{ + uint8_t test_FRFMSB = 0,test_FRFMID=0,test_FRFLSB=0; +#if 0 + SX1276Write( REG_LR_FRFMSB,Freq_Cal_Tab[3*ch]); + SX1276Write( REG_LR_FRFMID,Freq_Cal_Tab[3*ch+1]); + SX1276Write( REG_LR_FRFLSB,Freq_Cal_Tab[3*ch+2]); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB !=Freq_Cal_Tab[3*ch]) + return 0; + if(test_FRFMID !=Freq_Cal_Tab[3*ch+1]) + return 0; + if(test_FRFLSB !=Freq_Cal_Tab[3*ch+2]) + return 0; +#else + const uint32_t FXOSC = 32000000ul; + float fstep = FXOSC / 524288.0; + uint32_t freq = 470000000ul + ch * 1000000ul; + uint32_t frf = (uint32_t) (freq / fstep + 0.5); + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_FRFMSB, (frf >> 16) & 0xFF); + SX1276Write( REG_LR_FRFMID, (frf >> 8) & 0xFF); + SX1276Write( REG_LR_FRFLSB, (frf & 0xff)); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB != ((frf >> 16) & 0xFF)) + return 0; + if(test_FRFMID != ((frf >> 8) & 0xFF)) + return 0; + if(test_FRFLSB != (frf & 0xff)) + return 0; +#endif + + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFù +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +uint8_t LSD_RF_PoutSet(uint8_t power) +{ + LSD_RF_StandbyMode(); + SX1276Write( REG_LR_PACONFIG, 0xf0|power); + uint8_t test = 0; + SX1276Read(REG_LR_PACONFIG,&test); + if((0xf0|power)!=test) + return 0; + SX1276Write( REG_LR_PADAC, 0x80|RFLR_PADAC_20DBM_ON ); + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : ݷɺDIO0ӵ͵ƽɸߵƽÿεô˺ԶȽDIO0Ϊͣȴߵƽ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SendPacket(uint8_t*cbuf,uint8_t csize) +{ + unsigned long int j=0xFFFFFF; //ʱãûҪʵ + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_L; //ֹDIO0ж + SX1276_TxPacket(cbuf,csize); // + while((!(DIO0_IFG&DIO0_BIT))&&j)j--; //ȴGDIO0ƽΪ + DIO0_IFG_L; //жϱ־λ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : uint8_t cclen ɱݰЧ̶ݰʱΪֵ +// ز : +// ˵ : ɺDIO0ӵ͵ƽɸߵƽ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RXmode(uint8_t cclen) +{ + Rx_mode(cclen); //RFջлRXģʽ + //SX_DIO0_DIR = 0; // + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_H; //ʹDIO0ж +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFSleep״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SleepMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + //P1OUT &= ~BIT4; //PA_TX ʼΪ0 + //P1OUT &= ~BIT5; //PA_TX ʼΪ0 Ŀǽʹ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF CADʼ +// : +// ز : +// ˵ : DIO1--CADDetected DIO3---CADDone +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_CADinit(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0xf0); + SX1276Write( REG_LR_PREAMBLELSB,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK,\ + ~(RFLR_IRQFLAGS_CADDONE|RFLR_IRQFLAGS_CADDETECTED)); + // + SX1276Write( REG_LR_DIOMAPPING1,\ + RFLR_DIOMAPPING1_DIO3_00 | RFLR_DIOMAPPING1_DIO1_10); + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write(REG_LR_IRQFLAGS,0xff); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFCADŵһ +// : +// ز : +// ˵ : ʱԼΪ(2^SF+32)/BW +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_CAD_Sample(void) +{ + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_CAD ); +} +//////////////////////////////////////////////////////////////////////////////// +// : WORʼ +// : +// ز : +// ˵ : DIO1 :ж DIO3CADʱжϣҲΪǽռжϣ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WORInit(void) +{ + LSD_RF_CADinit(); //CADܳʼ + //CADDoneʹ + //SX_DIO3_DIR=0; // + DIO3_IFG_L; //DIO3־λ + DIO3_IES_L; //DIO3شʽ + DIO3_IE_H; //DIO3ж + //CADDetectedʹ + //SX_DIO1_DIR=0; // + DIO1_IFG_L; //DIO1־λ + DIO1_IES_L; //DIO1شʽ + DIO1_IE_H; //ʹDIO1ж + //رDIO0жʹ + DIO0_IE_L; //ʹDIO0ж +} +//////////////////////////////////////////////////////////////////////////////// +// : ִWOR +// : uint8_t cclen 0˯ߡ1CADģʽ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WOR_Execute(uint8_t cclen) +{ + switch(cclen) + { + case 0: //˯ + LSD_RF_SleepMode(); //˯ģʽ + ON_Sleep_Timerout(); //˯߳ʱʱ + break; + case 1: //CADģʽ + OFF_Sleep_Timerout(); //ر˯߳ʱʱ + LSD_RF_CAD_Sample(); //CADһ + + break; + default: break; + } +} +//////////////////////////////////////////////////////////////////////////////// +// : WORRX +// : +// ز : +// ˵ : ˳WORRXģʽǰpreambleȻֵ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WOR_Exit(uint8_t cclen) +{ + OFF_Sleep_Timerout(); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PAYLOADLENGTH,cclen); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); + //SX_DIO0_DIR = 0; // + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_H; //ʹDIO0ж + + DIO1_IE_L; //ֹDIO1 + DIO3_IE_L; //ֹDIO3 + +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFͻѰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_Awake(uint8_t*cbuf,uint8_t csize) +{ + //SX_DIO0_DIR = 0; + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_L; //ֹDIO0ж + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PAYLOADLENGTH,csize); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,cbuf,csize); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_PREAMBLEMSB,0x03);//set preamble length + SX1276Write( REG_LR_PREAMBLELSB,0xEC);//set preamble length + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); + while((!DIO0_IFG)); //ȴGDIO0ƽΪ + + DIO0_IFG_L; //жϱ־λ + //껽ݰ󣬽ǰʱĻĬֵ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0);//set preamble length + SX1276Write( REG_LR_PREAMBLELSB,10);//set preamble length + +} + +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/20201203烧录版本/FR2433-RFSX.h b/RF-AP/20201203烧录版本/FR2433-RFSX.h new file mode 100644 index 0000000..37a798f --- /dev/null +++ b/RF-AP/20201203烧录版本/FR2433-RFSX.h @@ -0,0 +1,307 @@ +#ifndef FR2433_RFSX +#define FR2433_RFSX +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: Haybin.Wu@studio +// ļ: +// 汾 V1.0 +// : IAR v6.20 +// : Haybin +// : 2016.05 +// : API for FR4133 +// ޸־ +//////////////////////////////////////////////////////////////////////////////// +#include +#include + +//====================================================================================== +#define CPU_MCLK 8000000 +#define DelayUs(us) __delay_cycles((CPU_MCLK/1000000UL) * us) +#define DelayMs(ms) __delay_cycles((CPU_MCLK/1000UL) * ms) +//////////////////////////////////////////////////////////////////////////////// +//ֻ޸ +//SX1276 SPI I/O definitions +#define SPI_PSEL P1SEL0 +#define SPI_PDIR P1DIR +#define SPI_POUT P1OUT +#define SPI_SI_BIT BIT2 +#define SPI_SO_BIT BIT3 +#define SPI_CLK_BIT BIT1 + +#define SPI_NSS_BIT BIT0 +#define SPI_NSS_PDIR P1DIR +#define SPI_NSS_POUT P1OUT + +//DIO0 +#define DIO0_BIT BIT6 +#define DIO0_DIR P1DIR +#define DIO0_IFG P1IFG +#define DIO0_IES P1IES +#define DIO0_IE P1IE + +//DIO1 +#define DIO1_BIT BIT7 +#define DIO1_DIR P1DIR +#define DIO1_IFG P1IFG +#define DIO1_IES P1IES +#define DIO1_IE P1IE +//DIO3 +#define DIO3_BIT BIT4 +#define DIO3_DIR P2DIR +#define DIO3_IFG P2IFG +#define DIO3_IES P2IES +#define DIO3_IE P2IE +//RST +#define RST_BIT BIT1 +#define RST_PDIR P3DIR +#define RST_POUT P3OUT + +//////////////////////////////////////////////////////////////////////////////// +//SX1276 SPI I/O definitions + +//NSS +#define SPI_NSS_DIR_OUT SPI_NSS_PDIR |= SPI_NSS_BIT //Ƭѡ out +#define SPI_NSS_OUT_1 SPI_NSS_POUT |= SPI_NSS_BIT //1 +#define SPI_NSS_OUT_0 SPI_NSS_POUT &= (~SPI_NSS_BIT) //1 + +//DIO0 +#define DIO0_IFG_H DIO0_IFG |= DIO0_BIT +#define DIO0_IFG_L DIO0_IFG &= ~DIO0_BIT +#define DIO0_IES_H DIO0_IES |= DIO0_BIT +#define DIO0_IES_L DIO0_IES &= ~DIO0_BIT +#define DIO0_IE_H DIO0_IE |= DIO0_BIT +#define DIO0_IE_L DIO0_IE &= ~DIO0_BIT + +//DIO1 +#define DIO1_IFG_H DIO1_IFG |= DIO1_BIT +#define DIO1_IFG_L DIO1_IFG &= ~DIO1_BIT +#define DIO1_IES_H DIO1_IES |= DIO1_BIT +#define DIO1_IES_L DIO1_IES &= ~DIO1_BIT +#define DIO1_IE_H DIO1_IE |= DIO0_BIT +#define DIO1_IE_L DIO1_IE &= ~DIO1_BIT + +//DIO3 +#define DIO3_IFG_H DIO3_IFG |= DIO3_BIT +#define DIO3_IFG_L DIO3_IFG &= ~DIO3_BIT +#define DIO3_IES_H DIO3_IES |= DIO3_BIT +#define DIO3_IES_L DIO3_IES &= ~DIO3_BIT +#define DIO3_IE_H DIO3_IE |= DIO3_BIT +#define DIO3_IE_L DIO3_IE &= ~DIO3_BIT + +//////////////////////////////////////////////////////////////////////////////// +// : SX1276 I/O pins definitions +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Init_IO( void ) +{ + //DIO0ΪP2.0 + //P2DIR &= ~BIT0; + //P2OUT |= BIT0; // Configure DIO0 as pulled-up + //P2REN |= BIT0; // DIO0pull-up register enable + DIO0_DIR&=~DIO0_BIT; + DIO0_IES_L; // DIO0 Hi/Low edge + DIO0_IE_L; // DIO0 interrupt enabled + DIO0_IFG_L; // DIO0IFG cleared + + //DIO1ΪP2.1 + //P2DIR &= ~BIT1; + //P2OUT |= BIT1; // Configure DIO1 as pulled-up + //P2REN |= BIT1; // DIO1pull-up register enable + DIO1_DIR&=~DIO1_BIT; + DIO1_IES_L; // DIO1 Hi/Low edge + DIO1_IE_L; // DIO1 interrupt enabled + DIO1_IFG_L; // DIO1IFG cleared + + //DIO3ΪP2.3 + //P2DIR &= ~BIT3; + //P2OUT |= BIT3; // Configure DIO3 as pulled-up + //P2REN |= BIT3; // DIO3pull-up register enable + DIO3_DIR&=~DIO3_BIT; + DIO3_IES_L; // DIO3 Hi/Low edge + DIO3_IE_L; // DIO3 interrupt enabled + DIO3_IFG_L; // DIO3IFG cleared + + + //SX1276 SPI I/O definitions + // Configure SPI + //SPI SET + SPI_NSS_DIR_OUT; + SPI_NSS_OUT_1; // /CS disable + + // SPI option select + SPI_PSEL |= SPI_SI_BIT+SPI_SO_BIT+SPI_CLK_BIT; + + UCB0CTLW0 |= UCSWRST; // **Put state machine in reset** + UCB0CTLW0 |= UCMST|UCSYNC|UCCKPH|UCMSB; // 3-pin, 8-bit SPI master + // Clock polarity high, MSB + UCB0CTLW0 |= UCSSEL__SMCLK; // SMCLK + UCB0BR0 = 1; // /2,fBitClock = fBRCLK/(UCBRx+1). + UCB0BR1 = 0; // + UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** + + //SX1276 RESET I/O definitions + RST_PDIR |= RST_BIT; + RST_POUT |= RST_BIT; + +} + +//////////////////////////////////////////////////////////////////////////////// +// : ˯߳ʱʱ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void ON_Sleep_Timerout(void) +{ + + //Timer1_A3 setup + TA1R =0; //ʱ + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768; + TA0CTL |= TASSEL_1 | MC_1; //ʱʱ +} +//////////////////////////////////////////////////////////////////////////////// +// : ر˯߳ʱʱ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void OFF_Sleep_Timerout(void) +{ + //TA0R =0; //ʱ + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768; + TA0CTL = TASSEL_1 | MC_0; //رնʱ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF λ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Reset(void) +{ + RST_POUT &= ~RST_BIT; //ӲλIO0 + DelayMs(6); //ʱ + RST_POUT |= RST_BIT; //Ϊ1 + DelayMs(5); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ +// : uint8_t addr,Ĵַ uint8_t *buffer,ָ uint8_t sizeָ볤 +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +{ + uint8_t i; + SPI_PSEL |= SPI_SO_BIT;//SPIbugĹ쳣 + SPI_NSS_OUT_0; +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + UCB0IFG &= ~UCRXIFG; // Clear flag + UCB0TXBUF = (addr | 0x80); // Send address + while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish + UCB0IFG &= ~UCTXIFG; // Clear flag + for( i = 0; i < size; i++ ) + { + UCB0TXBUF = buffer[i]; // Send data + while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish + UCB0IFG &= ~UCTXIFG; + } +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + SPI_NSS_OUT_1; + SPI_PSEL &= ~SPI_SO_BIT;//SPIbugĹ쳣 +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ +// : uint8_t addr,Ĵַ uint8_t *buffer,洢ָ uint8_t sizeҪij +// ز : ݷص*buffer +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +{ + uint8_t i; + SPI_PSEL |= SPI_SO_BIT;//SPIbugĹ쳣 + SPI_NSS_OUT_0; +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + UCB0IFG &= ~UCRXIFG; // Clear flag + UCB0TXBUF = (addr & 0x7F); // Send address + while (!(UCB0IFG&UCTXIFG)); // Wait for end of addr byte TX + UCB0IFG &= ~UCTXIFG; // Clear flag + for( i = 0; i < size; i++ ) + { + UCB0TXBUF = 0; //Initiate next data RX + while (!(UCB0IFG&UCRXIFG)); // Wait for RX to finish + buffer[i] = UCB0RXBUF; // Store data from last data RX + //ȡUCB0RXBUFIFGԶReset + } +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + SPI_NSS_OUT_1; + SPI_PSEL &= ~SPI_SO_BIT;//SPIbugĹ쳣 + UCB0IFG=0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַд1ֽ +// : uint8_t addr,Ĵַ uint8_t data +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Write( uint8_t addr, uint8_t data ) +{ + SX1276WriteBuffer( addr, &data, 1 ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ1ֽ +// : uint8_t addr,Ĵַ uint8_t *dataݴ洢ַ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Read( uint8_t addr, uint8_t *data ) +{ + SX1276ReadBuffer( addr, data, 1 ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF FIFOд +// : uint8_t *buffer,ָ uint8_t size +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteFifo( uint8_t *buffer, uint8_t size ) +{ + SX1276WriteBuffer( 0, buffer, size ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF FIFO +// : uint8_t *buffer,ָ uint8_t size +// ز : uint8_t *buffer 洢ȡ +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276ReadFifo( uint8_t *buffer, uint8_t size ) +{ + SX1276ReadBuffer( 0, buffer, size ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF TX/RXPAл +// : bool txEnable л߼ +// ز : +// ˵ :棺ΪTX٣ΪRX ΪӲPAIO +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteRxTx( bool txEnable ) +{ + if( txEnable != 0 ) //Ϊ棬ΪTX + { + ; + } + else //Ϊ٣ΪRX + { + ; + } +} + +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/20201203烧录版本/RF-Module.c b/RF-AP/20201203烧录版本/RF-Module.c new file mode 100644 index 0000000..2823370 --- /dev/null +++ b/RF-AP/20201203烧录版本/RF-Module.c @@ -0,0 +1,491 @@ +// Haybin_Wu +// Shenitech-RD +// 2016.5 +// Built with IAR Embedded Workbench v6.2 +//****************************************************************************** +// Modify by Qian Xianghong +// 2020.10 +// ޸־ģɴںRF˫͸ģʽ +//****************************************************************************** +#include +#include +#include +#include +#include "FR2433-RFSX.h" +#include "RF_SX1276.h" + +// Ƶò +lora_param_t Lora_Param; + +#define TRAN_BUF_SIZE (1024) + +// UA1ӡ +char printBuf[200]; +void uart_print() +{ +#if 0 // ӡڵ2MD0MD1ģʽѡ + char *p = printBuf; + while(*p) + { + if(*p == '\n') // ǰӻس + { + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = '\r'; + } + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = *p++; + } +#endif +} + +// ɱĺ궨 +#define PRINTF(format, ...) \ +{ \ + snprintf(printBuf, sizeof(printBuf), format, ##__VA_ARGS__); \ + uart_print(); \ +} + +// UA0λݵbuf +uint8_t UA0_RxBuf[TRAN_BUF_SIZE] = {0}; +uint16_t UA0_RxBuf_Length = 0; +uint16_t UA0_RxBuf_offset = 0; +// UA0ճʱ +volatile uint8_t UA0_Rx_Timeout = 1; + +// RFݵbuf +uint8_t RF_RxBuf[TRAN_BUF_SIZE] = {0}; +uint16_t RF_RxBuf_Length = 0; +uint16_t RF_RxBuf_offset = 0; +// RFճʱ־ +volatile uint8_t RF_Rx_Timeout = 1; + +//////////////////////////////////////////////////////////////////////////////// +// ڳʼ +void UA0_Init(uint32_t baudrate) +{ + // Configure UART + UCA0CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + if(baudrate == 115200) + { + UCA0BR0 = 4; // 8000000/16/115200//λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.44444 + UCA0MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢Baud Rate + } + else if(baudrate == 38400) + { + UCA0BR0 = 13; // 8000000/16/38400 /λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.33333 + UCA0MCTLW = 0x8400 | UCOS16 | UCBRF_0;//΢Baud Rate + } + else + { + UCA0BR0 = 52; // 8000000/16/9600 /λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.33333 + UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1;//΢Baud Rate + } + UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt +} + +// Ӧ +void UA0_Response(char *s) +{ + while(*s) + { + while(!(UCA0IFG & UCTXIFG)); + UCA0TXBUF = *s++; + } + // ȴͽ + while(!(UCA0IFG & UCTXCPTIFG)); + DelayMs(2); +} + +//////////////////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////////////////// + int main(void) +{ + uint8_t sendCh; + + WDTCTL = (WDTPW | WDTHOLD); // Stop WDT + // Port Configuration all un-used pins to output low + P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; + P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; + PM5CTL0 &= ~LOCKLPM5;//Ź + + // Configure DCO Clock + //ⲿʱԴ + P2SEL0 |= (BIT0 | BIT1); // set XT1 pin as second function + do + { + CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag + SFRIFG1 &= ~OFIFG; + } while (SFRIFG1 & OFIFG); // Test oscillator fault flag + //־ڽ͹ + + __bis_SR_register(SCG0); // disable FLL + CSCTL3 |= SELREF__XT1CLK; // ⲿ 32768hz reference source + CSCTL0 = 0; // clear DCO and MOD registers + CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first + CSCTL1 |= DCORSEL_3; //DCO=8Mhz + CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz + __delay_cycles(3); + __bic_SR_register(SCG0); // enable FLL + while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked + + CSCTL4 = SELREF__XT1CLK + SELMS__DCOCLKDIV;// set XT1CLK(32768Hz) as ACLK source & MCLK/SMCLK=DCO + + //Timer0_A0 setup + TA0CCTL0 = CCIE; // TACCR0 interrupt enabled + TA0CCR0 = 32768 / 32; // ڽճʱ: 1000/32=31.25ms + TA0CTL = MC__STOP | TACLR; // Stop mode, Clear counter + + //Timer1_A0 setup + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768 / 4; // RFճʱ: 1000/4=250ms + TA1CTL = MC__STOP | TACLR; // Stop mode, Clear counter + + // ģȱʡ + Lora_Param.sof = 0xC2; + Lora_Param.addr = 0xADF2; // ͨŵַ0xADF2 + Lora_Param.sf = 6; // sf=12 + Lora_Param.baud = 3; // 9600 + Lora_Param.cr = 0; // cr=4/5 + Lora_Param.ch = 9; // 479MHz + Lora_Param.power = 1; // 17dBm + Lora_Param.freqcast = 0; // freqcast off + Lora_Param.bw = 9; // 500kHz + Lora_Param.unicast = 0; // unicast off + + // Configure UART pins + P1SEL1 &= ~(BIT4 | BIT5); // set 2-UART pin as second function + P1SEL0 |= (BIT4 | BIT5); // set 2-UART pin as second function + if(Lora_Param.baud == 7) + UA0_Init(115200); + else if(Lora_Param.baud == 5) + UA0_Init(38400); + else + UA0_Init(9600); + +#if 0 // ôӡ + // Configure UART pins + P2SEL1 &= ~(BIT5 | BIT6); // set 2-UART pin as second function + P2SEL0 |= (BIT5 | BIT6); // set 2-UART pin as second function + // Configure UART + UCA1CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + UCA1BR0 = 4; // 8000000/16/115200//λ16 UCOS16λҪλ + UCA1BR1 = 0; // Fractional portion = 0.44444 + UCA1MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢Baud Rate + UCA1CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt + + // ӡλԭ(Դ𣬲Ź) + PRINTF("\nModule reseted: %04X\n", PMMIFG); + +#else // MD0MD1ģʽ + P2SEL1 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO + P2SEL0 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO + P2DIR &= ~(BIT5 | BIT6); // Input + P2REN |= (BIT5 | BIT6); // enable pull + P2OUT &= ~(BIT5 | BIT6); // pull-down + + P2DIR |= BIT3; // Output + P2OUT |= BIT3; // Output high +#endif + + _EINT(); + +#if 0 + // ӡλԭ(Դ𣬲Ź) + RF_RxBuf[0] = PMMIFG >> 8; + RF_RxBuf[1] = PMMIFG & 0xFF; + RF_RxBuf_Length = 2; + RF_RxBuf_offset = 0; + UCA0IE |= UCTXIE; + while(UCA0IE & UCTXIE); +#endif + // Ĵλԭ + SYSRSTIV; + + //ģʼ + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + // ʼڽģʽ + LSD_RF_RXmode(RF_PAYLOAD_LEN); + // ĬϷŵ + sendCh = Lora_Param.ch; + + // Ź: ʱʱΪ2^27/SMCLK8000000ƵԼΪ16s + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + while(1) + { +#if 1 + // TODO: ι + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + // ģʽ + if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6)) + { + if(UA0_RxBuf_Length - UA0_RxBuf_offset >= sizeof(Lora_Param)) + { + if(UA0_RxBuf[UA0_RxBuf_offset] == 0xC2) + { + // + memmove(&Lora_Param, UA0_RxBuf + UA0_RxBuf_offset, sizeof(Lora_Param)); + // ߵַߵֽ + Lora_Param.addr = (Lora_Param.addr << 8) | (Lora_Param.addr >> 8); + + //ģʼ + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + // б仯ģʼ + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + // Ĭϴڽģʽ + LSD_RF_RXmode(RF_PAYLOAD_LEN); + // ĬϷŵ + sendCh = Lora_Param.ch; + // Ӧ + UA0_Response("OK\r\n"); + + // ı䴮ڲ + if(Lora_Param.baud == 7) + UA0_Init(115200); + else if(Lora_Param.baud == 5) + UA0_Init(38400); + else + UA0_Init(9600); + } + + UA0_RxBuf_offset = UA0_RxBuf_Length; + } + } + // ͸ģʽ + else if((P2IN & (BIT5 | BIT6)) == 0) +#endif + { + if(UA0_RxBuf_Length > UA0_RxBuf_offset) + { + // 㴫䣬ָĿַŵ + if(Lora_Param.unicast) // 㷢 + { + if(UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 3) + sendCh = UA0_RxBuf[2]; + } + else if(Lora_Param.freqcast) // ָŵ + { + if(UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 1) + { + sendCh = UA0_RxBuf[0]; + UA0_RxBuf_offset = 1; // ͵1ֽ + } + } + + if(UA0_RxBuf_Length - UA0_RxBuf_offset >= RF_PAYLOAD_LEN) + { + LSD_RF_FreqSet(sendCh); + LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, RF_PAYLOAD_LEN); + UA0_RxBuf_offset += RF_PAYLOAD_LEN; + PRINTF("Send packet\n"); + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + + } + else if(UA0_Rx_Timeout) + { + LSD_RF_FreqSet(sendCh); + LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, UA0_RxBuf_Length - UA0_RxBuf_offset); + UA0_RxBuf_offset = UA0_RxBuf_Length; + PRINTF("Send packet\n"); + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + } + } + } + + if(UA0_Rx_Timeout && UA0_RxBuf_offset == UA0_RxBuf_Length) + P2OUT |= BIT3; // Output high + } +} + +// Port 1 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=PORT1_VECTOR +__interrupt void Port_1(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(PORT1_VECTOR))) Port_1 (void) +#else +#error Compiler not supported! +#endif +{ + uint8_t offset = 0; + uint8_t len[1] = {0}; + uint8_t buf[RF_PAYLOAD_LEN]; + if(DIO0_IFG&DIO0_BIT) //ݴжϴ + { + // ж + DIO0_IFG &= ~DIO0_BIT; + + // ȡRF + LSD_RF_RxVariPacket(buf, len); //տɱݰΪʣֻýչ̶ݰ + + if(len[0] == 0) + return; + + TA1CTL = MC__STOP | TACLR; // ֹͣʱλ + TA1CTL = TASSEL__ACLK | MC__UP; // ¿ʼʱ + + offset = 0; + if(RF_Rx_Timeout) // µһݵ + { + RF_Rx_Timeout = 0; + + // λ + RF_RxBuf_Length = 0; + RF_RxBuf_offset = 0; + + if(Lora_Param.unicast) + { + // 㴫䣬ַŵУʧ + if(len[0] <= 3 || buf[2] != Lora_Param.ch || ((buf[0] << 8) | buf[1]) != Lora_Param.addr) + return; + // ǰ3ַ + offset = 3; + len[0] -= offset; + } + } + + PRINTF("Recv packet\n"); + + // ͸ģʽ + if((P2IN & (BIT5 | BIT6)) == 0) + { + if(RF_RxBuf_Length + len[0] <= TRAN_BUF_SIZE) + { + memmove(RF_RxBuf + RF_RxBuf_Length, buf + offset, len[0]); + // жϷʽ򴮿ת + RF_RxBuf_Length += len[0]; + UCA0IE |= UCTXIE; + } + } + } +} + +// Timer0 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER0_A0_VECTOR +__interrupt void Timer0_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) Timer0_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ֹͣʱλ + TA0CTL = MC__STOP | TACLR; + // ڽճʱ + UA0_Rx_Timeout = 1; +} + +// Timer1 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER1_A0_VECTOR +__interrupt void Timer1_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER1_A0_VECTOR))) Timer1_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ֹͣʱλ + TA1CTL = MC__STOP | TACLR; + // RFճʱ + RF_Rx_Timeout = 1; +} + +// UAR0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=USCI_A0_VECTOR +__interrupt void USCI_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ж + if((UCA0IE & UCRXIE) && (UCA0IFG & UCRXIFG)) + { + uint8_t c = UCA0RXBUF; + + TA0CTL = MC__STOP | TACLR; // ֹͣʱλ + TA0CTL = TASSEL__ACLK | MC__UP; // ¿ʼʱ + + if(UA0_Rx_Timeout) // µһݵ + { + UA0_Rx_Timeout = 0; + // λ + UA0_RxBuf_Length = 0; + UA0_RxBuf_offset = 0; + } + + if(UA0_RxBuf_Length < TRAN_BUF_SIZE) + { +#if 1 + // ģʽ + if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6)) + { + // 1ַΪ0xC2 + if(UA0_RxBuf_Length > 0 || c == 0xC2) + UA0_RxBuf[UA0_RxBuf_Length++] = c; + } + // ͸ģʽ + else if((P2IN & (BIT5 | BIT6)) == 0) +#endif + { + // ͸ + UA0_RxBuf[UA0_RxBuf_Length++] = c; + } + + P2OUT &= ~BIT3; // Output low + } + } + + // ж + if((UCA0IE & UCTXIE) && (UCA0IFG & UCTXIFG)) + { + UCA0TXBUF = RF_RxBuf[RF_RxBuf_offset++]; // ַ + if(RF_RxBuf_offset >= RF_RxBuf_Length) // ȫ + { + // ֹж + UCA0IE &= ~UCTXIE; + } + } +} diff --git a/RF-AP/20201203烧录版本/RF_SX1276.h b/RF-AP/20201203烧录版本/RF_SX1276.h new file mode 100644 index 0000000..9869a81 --- /dev/null +++ b/RF-AP/20201203烧录版本/RF_SX1276.h @@ -0,0 +1,1295 @@ +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: Haybin.Wu@studio +// ļ: +// 汾 V1.0 +// : IAR v6.20 +// : Haybin +// : 2016.05 +// : API +// ޸־ +//////////////////////////////////////////////////////////////////////////////// +// Modify by Qian Xianghong +// 2020.10 +// ޸־ +// 1. LSD_RF_SendPacket(): +// ޸жDIO0־ȷɣúʱ +// ǰ볤޸Ϊ8.Ĭֵмһ£ +// 2. LSD_RF_RXmode(): +// PayloadCrcErrorʶ +// ǰ볤޸Ϊ8.Ĭֵмһ£ +// 3. LSD_RF_RxVariPacket(): +// жRxDonePayloadCRCErrorʶ +// ȶȡREG_LR_FIFORXCURRENTADDRĴֵٴӸõַʼȡݡ +// 4. LSD_RF_RxFixiPacket(): +// жRxDonePayloadCRCErrorʶ +// 5. SX127x_initLora()ڸسʼLoRa +//////////////////////////////////////////////////////////////////////////////// +#include +#include +#include "FR2433-RFSX.h" +#ifndef RF_SX1276 +#define RF_SX1276 + +uint8_t LSD_RF_FreqSet(uint8_t ch); +uint8_t LSD_RF_PoutSet(uint8_t power); +//====================================================================================== +#define RF_PAYLOAD_LEN (64) + +#pragma pack(push, 1) +// LORAҫ +typedef struct +{ + uint8_t sof; // ǰ룬̶Ϊ0xC2 + uint16_t addr; // ͨŵַ + unsigned char sf : 3; // Ƶ: 0-1-7,...,6-12,7- + unsigned char baud : 3; // ڲʣ3-9600,7-115200, ౣ + unsigned char cr : 2; // : 0-4/5,1-4/6,2-4/7,3-4/8 + uint8_t ch; // ͨŵ: 0~40(470M~510M),ౣ + unsigned char power : 2; // Power: 0-20dBm,1-17dBm,2-14dBm,3-11dBm + unsigned char freqcast: 1; // Ƿָŵ + unsigned char bw : 4; // 0-7.8kHz,1-10.4kHz,...,9-500kHz, ౣ + unsigned char unicast : 1; // Ƿ񶨵㷢 +} lora_param_t; +#pragma pack(pop) +//====================================================================================== +/*! + * SX1276 LoRa General parameters definition + */ +typedef struct sLoRaSettings +{ + uint32_t RFFrequency; + int8_t Power; + uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz, + // 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved] + uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips] + uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + bool CrcOn; // [0: OFF, 1: ON] + bool ImplicitHeaderOn; // [0: OFF, 1: ON] + bool RxSingleOn; // [0: Continuous, 1 Single] + bool FreqHopOn; // [0: OFF, 1: ON] + uint8_t HopPeriod; // Hops every frequency hopping period symbols + uint32_t TxPacketTimeout; + uint32_t RxPacketTimeout; + uint8_t PayloadLength; +}tLoRaSettings; + +/*! + * RF packet definition + */ +#define RF_BUFFER_SIZE_MAX 128 +#define RF_BUFFER_SIZE 80 + +/*! + * RF state machine + */ +//LoRa +typedef enum +{ + RFLR_STATE_IDLE, + RFLR_STATE_RX_INIT, + RFLR_STATE_RX_RUNNING, + RFLR_STATE_RX_DONE, + RFLR_STATE_RX_TIMEOUT, + RFLR_STATE_TX_INIT, + RFLR_STATE_TX_RUNNING, + RFLR_STATE_TX_DONE, + RFLR_STATE_TX_TIMEOUT, + RFLR_STATE_CAD_INIT, + RFLR_STATE_CAD_RUNNING, +}tRFLRStates; + +/*! + * SX1276 definitions + */ +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +/*! + * SX1276 Internal registers Address + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +//#define REG_LR_BANDSETTING 0x04 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_NBRXBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 + +/*! + * SX1276 LoRa bit control definition + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegBandSetting + */ +#define RFLR_BANDSETTING_MASK 0x3F +#define RFLR_BANDSETTING_AUTO 0x00 // Default +#define RFLR_BANDSETTING_DIV_BY_1 0x40 +#define RFLR_BANDSETTING_DIV_BY_2 0x80 +#define RFLR_BANDSETTING_DIV_BY_6 0xC0 + + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RFLR_LNA_BOOST_LF_GAIN 0x08 +#define RFLR_LNA_BOOST_LF_IP3 0x10 +#define RFLR_LNA_BOOST_LF_BOOST 0x18 +#define RFLR_LNA_RXBANDFORCE_MASK 0xFB +#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + + + +/*! + * RegFifoRxNbBytes (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueMsb (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueLsb (Read Only) // + */ + + +/*! + * RegRxPacketCntValueMsb (Read Only) // + */ + + + /*! + * RegRxPacketCntValueLsb (Read Only) // + */ + + + /*! + * RegModemStat (Read Only) // + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) // + */ + + + /*! + * RegPktRssiValue (Read Only) // + */ + + +/*! + * RegRssiValue (Read Only) // + */ + + + /*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F + +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + + /*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + + +/*! + * RegHopChannel (Read Only) + */ + +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40 +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegModemConfig3 + */ +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +/*! + * RegFormerTemp + */ + +typedef struct sSX1276LR +{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + + uint8_t RegTestReserved02[0x06 - 0x02]; // 0x02-0x05 + // uint8_t RegRes02; // 0x02 + // uint8_t RegRes03; // 0x03 + // uint8_t RegBandSetting; // 0x04 + // uint8_t RegRes05; // 0x05 + + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + // LoRa registers + uint8_t RegFifoAddrPtr; // 0x0D + uint8_t RegFifoTxBaseAddr; // 0x0E + uint8_t RegFifoRxBaseAddr; // 0x0F + uint8_t RegFifoRxCurrentAddr; // 0x10 + uint8_t RegIrqFlagsMask; // 0x11 + uint8_t RegIrqFlags; // 0x12 + uint8_t RegNbRxBytes; // 0x13 + uint8_t RegRxHeaderCntValueMsb; // 0x14 + uint8_t RegRxHeaderCntValueLsb; // 0x15 + uint8_t RegRxPacketCntValueMsb; // 0x16 + uint8_t RegRxPacketCntValueLsb; // 0x17 + uint8_t RegModemStat; // 0x18 + uint8_t RegPktSnrValue; // 0x19 + uint8_t RegPktRssiValue; // 0x1A + uint8_t RegRssiValue; // 0x1B + uint8_t RegHopChannel; // 0x1C + uint8_t RegModemConfig1; // 0x1D + uint8_t RegModemConfig2; // 0x1E + uint8_t RegSymbTimeoutLsb; // 0x1F + uint8_t RegPreambleMsb; // 0x20 + uint8_t RegPreambleLsb; // 0x21 + uint8_t RegPayloadLength; // 0x22 + uint8_t RegMaxPayloadLength; // 0x23 + uint8_t RegHopPeriod; // 0x24 + uint8_t RegFifoRxByteAddr; // 0x25 + uint8_t RegModemConfig3; // 0x26 + uint8_t RegTestReserved27[0x31 - 0x27]; // 0x27-0x30 + //void SX1276LoRaSetNbTrigPeaks( uint8_t value )õ + uint8_t RegTestReserved31; // 0x31 + uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x3F + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + + uint8_t RegTestReserved43[0x4B - 0x43]; // 0x43-0x4A + uint8_t RegTcxo; // 0x4B + uint8_t RegTestReserved4C; // 0x4C + uint8_t RegPaDac; // 0x4D + uint8_t RegTestReserved4E[0x5B - 0x4E]; // 0x4E-0x5A + uint8_t RegFormerTemp; // 0x5B + uint8_t RegTestReserved5C[0x61 - 0x5C]; // 0x5C-0x60 + // Additional settings + uint8_t RegAgcRef; // 0x61 + uint8_t RegAgcThresh1; // 0x62 + uint8_t RegAgcThresh2; // 0x63 + uint8_t RegAgcThresh3; // 0x64 + uint8_t RegTestReserved65[0x70 - 0x65]; // 0x65-0x6F + uint8_t RegPll; // 0x70 +}tSX1276LR; +////////////////////////////////////////////////////////////////////////////// +typedef enum +{ + Init_LoRa_0_8K, + Init_LoRa_4_8K, + Init_LoRa_10k, +}tSX127xInitPara; //ö + +typedef enum +{ + NORMAL, // + PARAMETER_INVALID, // + SPI_READCHECK_WRONG, //SPI +}tSX127xError; //ö + +typedef enum +{ + SLEEP, + STANDBY, + TX_ONGOING, + RX_ONGOING, +}tSX127xState; //RF״̬ûԲʹ + +typedef enum +{ + HOLDON, + TX, + LISTENING, +}tRadio_Machine; //߼״̬ûԲʹ + +typedef enum +{ + MASTER, + SLAVE, +}tMasterSlave; //ö ʱ + +typedef struct +{ + tMasterSlave MasterSlave; // + tSX127xState SX127xState; //״̬ + tRadio_Machine Machine; //߼״̬ +}stRadio_Situation; //״̬ṹ + +const unsigned char Freq_Cal_Tab[]= +{ + 0x75,0x80,0x00,//470MHz + 0x75,0xC0,0x00,//471MHz + 0x76,0x00,0x00,//472MHz + 0x76,0x40,0x00,//473MHz + 0x76,0x80,0x00,//474MHz + 0x76,0xC0,0x00,//475MHz + 0x77,0x00,0x00,//476MHz + 0x77,0x40,0x00,//477MHz + 0x77,0x80,0x00,//478MHz + 0x77,0xC0,0x00,//479MHz + 0x78,0x00,0x00,//480MHz + 0x78,0x40,0x00,//481MHz + 0x78,0x80,0x00,//482MHz + 0x78,0xC0,0x00,//483MHz + 0x79,0x00,0x00,//484MHz + 0x79,0x40,0x00,//485MHz + 0x79,0x80,0x00,//486MHz + 0x79,0xC0,0x00,//487MHz + 0x7A,0x00,0x00,//488MHz + 0x7A,0x40,0x00,//489MHz + 0x7A,0x80,0x00,//490MHz + 0x7A,0xC0,0x00,//491MHz + 0x7B,0x00,0x00,//492MHz + 0x7B,0x40,0x00,//493MHz + 0x7B,0x80,0x00,//494MHz + 0x7B,0xC0,0x00,//495MHz + 0x7C,0x00,0x00,//496MHz + 0x7C,0x40,0x00,//497MHz + 0x7C,0x80,0x00,//498MHz + 0x7C,0xC0,0x00,//499MHz + 0x7D,0x00,0x00,//500MHz + 0x7D,0x40,0x00,//501MHz + 0x7D,0x80,0x00,//502MHz + 0x7D,0xC0,0x00,//503MHz + 0x7E,0x00,0x00,//504MHz + 0x7E,0x40,0x00,//505MHz + 0x7E,0x80,0x00,//506MHz + 0x7E,0xC0,0x00,//507MHz + 0x7F,0x00,0x00,//508MHz + 0x7F,0x40,0x00,//509MHz + 0x7F,0x80,0x00,//510MHz +}; + +//extern stRadio_Situation SX127xSituation; +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : tSX127xInitPara initPara Init_LoRa_0_8K, Init_LoRa_4_8K , Init_LoRa_10k, +// ز : tSX127xError ö +// ˵ : ʼʱŵʼĬΪ0ŵ +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_init(tSX127xInitPara initPara) +{ + uint8_t test = 0; + if(initPara>Init_LoRa_10k) // + { + return PARAMETER_INVALID; // + } + SX1276Init_IO(); // PAIOڳʼ + SX1276Reset(); //λRF + //init Regs + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PACONFIG, 0xff ); + SX1276Write( REG_LR_PADAC, RFLR_PADAC_20DBM_ON ); + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US); + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA); + SX1276Write( REG_LR_PAYLOADLENGTH,2); + SX1276Write( REG_LR_MODEMCONFIG3,\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON| + RFLR_MODEMCONFIG3_AGCAUTO_ON); + //BW,SF,CR,Header,CRC +// SX1276Write( REG_LR_MODEMCONFIG2,0xFF); +// SX1276Write( REG_LR_SYMBTIMEOUTLSB,0xFF); + switch(initPara){ + case Init_LoRa_0_8K: +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON| +// RFLR_MODEMCONFIG3_AGCAUTO_ON); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_125_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_9|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); + SX1276Write( REG_LR_PREAMBLELSB,10); + SX1276Write(0x31,0x55); + SX1276Read( 0x31,&test); + break; + case Init_LoRa_4_8K: +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF| +// RFLR_MODEMCONFIG3_AGCAUTO_OFF); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_8|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); +// SX1276Write( REG_LR_PREAMBLEMSB,1); + SX1276Write( REG_LR_PREAMBLELSB,10); + break; + case Init_LoRa_10k: + SX1276Read( 0x31,&test); + SX1276Write( 0x31,(test& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF| +// RFLR_MODEMCONFIG3_AGCAUTO_ON); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_ON); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_6|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); +// SX1276Write( REG_LR_PREAMBLEMSB,4); + SX1276Write( REG_LR_PREAMBLELSB,10); + break; + default: + break; + } + if(!LSD_RF_FreqSet(1)) //Ϊ0ŵ + return SPI_READCHECK_WRONG; + + return NORMAL; +} + +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : lora_param_t lora +// ز : tSX127xError ö +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_initLora(lora_param_t *lora) +{ + static uint8_t first = 1; + + // + if(lora->sof != 0xC2 || lora->sf > 6 || (lora->baud != 3 && lora->baud != 5 && lora->baud != 7) || lora->ch > 40 || lora->bw > 9) + return PARAMETER_INVALID; + + if(first) + { + first = 0; + SX1276Init_IO(); // PAIOڳʼ + } + SX1276Reset(); //λRF + + //лLoRamodestandby״̬ + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + + /*------------------------------------------------ + SPI ֤ */ + uint8_t test = 0; + SX1276Write( REG_LR_HOPPERIOD,0x91 );//ѡһòļĴ֤ + SX1276Read( REG_LR_HOPPERIOD,&test); + if(test!=0x91) + return SPI_READCHECK_WRONG; + + SX1276Write( REG_LR_PACONFIG, 0xff ); + + //Frequency Configuration + LSD_RF_FreqSet(lora->ch); //Ƶ + //PA Configuration + switch(lora->power) + { + case 0: // 20dBm + LSD_RF_PoutSet(15); + break; + case 1: // 17dBm + LSD_RF_PoutSet(15); + break; + case 2: // 14dBm + LSD_RF_PoutSet(12); + break; + case 3: // 11dBm + LSD_RF_PoutSet(9); + break; + } + + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US); + // PA Rampʱ䣬ûLDOܿʵPA Rampʱ + // Rampʱ̳LDOʱֽTXϵͳΪRFźŲֵ + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);//ر Over Current Protection + + //PayloadLength ʼ + SX1276Write( REG_LR_PAYLOADLENGTH, RF_PAYLOAD_LEN); + //ע⣬ͷģʽImplicit Headerʱǰ涨շ˫PL + + //BWCRImplictHeader_On (SF6) / Off (SF7~12) + SX1276Write( REG_LR_MODEMCONFIG1,\ + (((uint8_t)(lora->bw << 4)) | ((uint8_t) ((lora->cr + 1) << 1))) | (lora->sf == 0 ? 0x01 : 0x00)); + + //SFPayloadCrc_Off + SX1276Write( REG_LR_MODEMCONFIG2,\ + ((uint8_t)((lora->sf + 6) << 4)) | 0x40); + + uint8_t temp = 0; + SX1276Read( 0x31,&temp); + if(0 == lora->sf) //SF = 6Ҫú + { + SX1276Write( 0x31,(temp& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); + } + else + { + SX1276Write( 0x31,(temp& 0xF8)|0x03); + SX1276Write( 0x37,0x0A); + } + + //ŻǷAutoAGCĬϿ + // SF12500kHz£뿪ʺܸ + SX1276Write( REG_LR_MODEMCONFIG3,(\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON\ + )|RFLR_MODEMCONFIG3_AGCAUTO_ON); + + // Ƶѡ + SX1276Write( REG_LR_DIOMAPPING2, RFLR_DIOMAPPING2_DIO4_01); + + return NORMAL; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : Ϊǣ preambleĻĬֵ +//////////////////////////////////////////////////////////////////////////////// +void SX1276_TxPacket(uint8_t*data,uint8_t size) +{ + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,8); + SX1276Write( REG_LR_PAYLOADLENGTH,size); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,data,size); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE_MASK)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : uint8_t clen ɱݰ´ֵЧ̶ݰΪֵ +// ز : +// ˵ : պpreambleûĬֵΪ +//////////////////////////////////////////////////////////////////////////////// +void Rx_mode(uint8_t clen) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,8); + SX1276Write( REG_LR_PAYLOADLENGTH,clen); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE_MASK | RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFտɱݰ +// : uint8_t*cbufָ,uint8_t *csizeسָ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxVariPacket(uint8_t*cbuf,uint8_t *csize) +{ + uint8_t flag, ptr; + + SX1276Read(REG_LR_IRQFLAGS, &flag); + + SX1276Read(REG_LR_FIFORXCURRENTADDR, &ptr); + SX1276Read(REG_LR_NBRXBYTES,csize); + SX1276Write( REG_LR_FIFOADDRPTR,ptr); + SX1276ReadFifo(cbuf,*csize); + SX1276Write(REG_LR_IRQFLAGS,0xff); + + if(!(flag & RFLR_IRQFLAGS_RXDONE) || (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR)) + *csize = 0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RFչ̶ݰ +// : uint8_t*cbufָ,uint8_t csizeչ̶ +// ز : +// ˵ : 10kʱֻܲù̶ݰ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxFixiPacket(uint8_t*cbuf,uint8_t *csize) +{ + uint8_t flag; + + SX1276Read(REG_LR_IRQFLAGS, &flag); + + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276ReadFifo(cbuf,*csize); + SX1276Write(REG_LR_IRQFLAGS,0xff); + + if(!(flag & RFLR_IRQFLAGS_RXDONE) || (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR)) + *csize = 0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RFstandby״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_StandbyMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF벻ͬŵ +// : uint8_t ch Χ0-40 +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +uint8_t LSD_RF_FreqSet(uint8_t ch) +{ + uint8_t test_FRFMSB = 0,test_FRFMID=0,test_FRFLSB=0; +#if 0 + SX1276Write( REG_LR_FRFMSB,Freq_Cal_Tab[3*ch]); + SX1276Write( REG_LR_FRFMID,Freq_Cal_Tab[3*ch+1]); + SX1276Write( REG_LR_FRFLSB,Freq_Cal_Tab[3*ch+2]); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB !=Freq_Cal_Tab[3*ch]) + return 0; + if(test_FRFMID !=Freq_Cal_Tab[3*ch+1]) + return 0; + if(test_FRFLSB !=Freq_Cal_Tab[3*ch+2]) + return 0; +#else + const uint32_t FXOSC = 32000000ul; + float fstep = FXOSC / 524288.0; + uint32_t freq = 470000000ul + ch * 1000000ul; + uint32_t frf = (uint32_t) (freq / fstep + 0.5); + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_FRFMSB, (frf >> 16) & 0xFF); + SX1276Write( REG_LR_FRFMID, (frf >> 8) & 0xFF); + SX1276Write( REG_LR_FRFLSB, (frf & 0xff)); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB != ((frf >> 16) & 0xFF)) + return 0; + if(test_FRFMID != ((frf >> 8) & 0xFF)) + return 0; + if(test_FRFLSB != (frf & 0xff)) + return 0; +#endif + + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFù +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +uint8_t LSD_RF_PoutSet(uint8_t power) +{ + LSD_RF_StandbyMode(); + SX1276Write( REG_LR_PACONFIG, 0xf0|power); + uint8_t test = 0; + SX1276Read(REG_LR_PACONFIG,&test); + if((0xf0|power)!=test) + return 0; + SX1276Write( REG_LR_PADAC, 0x80|RFLR_PADAC_20DBM_ON ); + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : ݷɺDIO0ӵ͵ƽɸߵƽÿεô˺ԶȽDIO0Ϊͣȴߵƽ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SendPacket(uint8_t*cbuf,uint8_t csize) +{ + unsigned long int j=0xFFFFFF; //ʱãûҪʵ + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_L; //ֹDIO0ж + SX1276_TxPacket(cbuf,csize); // + while((!(DIO0_IFG&DIO0_BIT))&&j)j--; //ȴGDIO0ƽΪ + DIO0_IFG_L; //жϱ־λ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : uint8_t cclen ɱݰЧ̶ݰʱΪֵ +// ز : +// ˵ : ɺDIO0ӵ͵ƽɸߵƽ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RXmode(uint8_t cclen) +{ + Rx_mode(cclen); //RFջлRXģʽ + //SX_DIO0_DIR = 0; // + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_H; //ʹDIO0ж +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFSleep״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SleepMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + //P1OUT &= ~BIT4; //PA_TX ʼΪ0 + //P1OUT &= ~BIT5; //PA_TX ʼΪ0 Ŀǽʹ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF CADʼ +// : +// ز : +// ˵ : DIO1--CADDetected DIO3---CADDone +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_CADinit(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0xf0); + SX1276Write( REG_LR_PREAMBLELSB,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK,\ + ~(RFLR_IRQFLAGS_CADDONE|RFLR_IRQFLAGS_CADDETECTED)); + // + SX1276Write( REG_LR_DIOMAPPING1,\ + RFLR_DIOMAPPING1_DIO3_00 | RFLR_DIOMAPPING1_DIO1_10); + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write(REG_LR_IRQFLAGS,0xff); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFCADŵһ +// : +// ز : +// ˵ : ʱԼΪ(2^SF+32)/BW +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_CAD_Sample(void) +{ + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_CAD ); +} +//////////////////////////////////////////////////////////////////////////////// +// : WORʼ +// : +// ز : +// ˵ : DIO1 :ж DIO3CADʱжϣҲΪǽռжϣ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WORInit(void) +{ + LSD_RF_CADinit(); //CADܳʼ + //CADDoneʹ + //SX_DIO3_DIR=0; // + DIO3_IFG_L; //DIO3־λ + DIO3_IES_L; //DIO3شʽ + DIO3_IE_H; //DIO3ж + //CADDetectedʹ + //SX_DIO1_DIR=0; // + DIO1_IFG_L; //DIO1־λ + DIO1_IES_L; //DIO1شʽ + DIO1_IE_H; //ʹDIO1ж + //رDIO0жʹ + DIO0_IE_L; //ʹDIO0ж +} +//////////////////////////////////////////////////////////////////////////////// +// : ִWOR +// : uint8_t cclen 0˯ߡ1CADģʽ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WOR_Execute(uint8_t cclen) +{ + switch(cclen) + { + case 0: //˯ + LSD_RF_SleepMode(); //˯ģʽ + ON_Sleep_Timerout(); //˯߳ʱʱ + break; + case 1: //CADģʽ + OFF_Sleep_Timerout(); //ر˯߳ʱʱ + LSD_RF_CAD_Sample(); //CADһ + + break; + default: break; + } +} +//////////////////////////////////////////////////////////////////////////////// +// : WORRX +// : +// ز : +// ˵ : ˳WORRXģʽǰpreambleȻֵ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WOR_Exit(uint8_t cclen) +{ + OFF_Sleep_Timerout(); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PAYLOADLENGTH,cclen); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); + //SX_DIO0_DIR = 0; // + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_H; //ʹDIO0ж + + DIO1_IE_L; //ֹDIO1 + DIO3_IE_L; //ֹDIO3 + +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFͻѰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_Awake(uint8_t*cbuf,uint8_t csize) +{ + //SX_DIO0_DIR = 0; + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_L; //ֹDIO0ж + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PAYLOADLENGTH,csize); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,cbuf,csize); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_PREAMBLEMSB,0x03);//set preamble length + SX1276Write( REG_LR_PREAMBLELSB,0xEC);//set preamble length + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); + while((!DIO0_IFG)); //ȴGDIO0ƽΪ + + DIO0_IFG_L; //жϱ־λ + //껽ݰ󣬽ǰʱĻĬֵ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0);//set preamble length + SX1276Write( REG_LR_PREAMBLELSB,10);//set preamble length + +} + +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/FR2433-RFSX.h b/RF-AP/FR2433-RFSX.h new file mode 100644 index 0000000..37a798f --- /dev/null +++ b/RF-AP/FR2433-RFSX.h @@ -0,0 +1,307 @@ +#ifndef FR2433_RFSX +#define FR2433_RFSX +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: Haybin.Wu@studio +// ļ: +// 汾 V1.0 +// : IAR v6.20 +// : Haybin +// : 2016.05 +// : API for FR4133 +// ޸־ +//////////////////////////////////////////////////////////////////////////////// +#include +#include + +//====================================================================================== +#define CPU_MCLK 8000000 +#define DelayUs(us) __delay_cycles((CPU_MCLK/1000000UL) * us) +#define DelayMs(ms) __delay_cycles((CPU_MCLK/1000UL) * ms) +//////////////////////////////////////////////////////////////////////////////// +//ֻ޸ +//SX1276 SPI I/O definitions +#define SPI_PSEL P1SEL0 +#define SPI_PDIR P1DIR +#define SPI_POUT P1OUT +#define SPI_SI_BIT BIT2 +#define SPI_SO_BIT BIT3 +#define SPI_CLK_BIT BIT1 + +#define SPI_NSS_BIT BIT0 +#define SPI_NSS_PDIR P1DIR +#define SPI_NSS_POUT P1OUT + +//DIO0 +#define DIO0_BIT BIT6 +#define DIO0_DIR P1DIR +#define DIO0_IFG P1IFG +#define DIO0_IES P1IES +#define DIO0_IE P1IE + +//DIO1 +#define DIO1_BIT BIT7 +#define DIO1_DIR P1DIR +#define DIO1_IFG P1IFG +#define DIO1_IES P1IES +#define DIO1_IE P1IE +//DIO3 +#define DIO3_BIT BIT4 +#define DIO3_DIR P2DIR +#define DIO3_IFG P2IFG +#define DIO3_IES P2IES +#define DIO3_IE P2IE +//RST +#define RST_BIT BIT1 +#define RST_PDIR P3DIR +#define RST_POUT P3OUT + +//////////////////////////////////////////////////////////////////////////////// +//SX1276 SPI I/O definitions + +//NSS +#define SPI_NSS_DIR_OUT SPI_NSS_PDIR |= SPI_NSS_BIT //Ƭѡ out +#define SPI_NSS_OUT_1 SPI_NSS_POUT |= SPI_NSS_BIT //1 +#define SPI_NSS_OUT_0 SPI_NSS_POUT &= (~SPI_NSS_BIT) //1 + +//DIO0 +#define DIO0_IFG_H DIO0_IFG |= DIO0_BIT +#define DIO0_IFG_L DIO0_IFG &= ~DIO0_BIT +#define DIO0_IES_H DIO0_IES |= DIO0_BIT +#define DIO0_IES_L DIO0_IES &= ~DIO0_BIT +#define DIO0_IE_H DIO0_IE |= DIO0_BIT +#define DIO0_IE_L DIO0_IE &= ~DIO0_BIT + +//DIO1 +#define DIO1_IFG_H DIO1_IFG |= DIO1_BIT +#define DIO1_IFG_L DIO1_IFG &= ~DIO1_BIT +#define DIO1_IES_H DIO1_IES |= DIO1_BIT +#define DIO1_IES_L DIO1_IES &= ~DIO1_BIT +#define DIO1_IE_H DIO1_IE |= DIO0_BIT +#define DIO1_IE_L DIO1_IE &= ~DIO1_BIT + +//DIO3 +#define DIO3_IFG_H DIO3_IFG |= DIO3_BIT +#define DIO3_IFG_L DIO3_IFG &= ~DIO3_BIT +#define DIO3_IES_H DIO3_IES |= DIO3_BIT +#define DIO3_IES_L DIO3_IES &= ~DIO3_BIT +#define DIO3_IE_H DIO3_IE |= DIO3_BIT +#define DIO3_IE_L DIO3_IE &= ~DIO3_BIT + +//////////////////////////////////////////////////////////////////////////////// +// : SX1276 I/O pins definitions +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Init_IO( void ) +{ + //DIO0ΪP2.0 + //P2DIR &= ~BIT0; + //P2OUT |= BIT0; // Configure DIO0 as pulled-up + //P2REN |= BIT0; // DIO0pull-up register enable + DIO0_DIR&=~DIO0_BIT; + DIO0_IES_L; // DIO0 Hi/Low edge + DIO0_IE_L; // DIO0 interrupt enabled + DIO0_IFG_L; // DIO0IFG cleared + + //DIO1ΪP2.1 + //P2DIR &= ~BIT1; + //P2OUT |= BIT1; // Configure DIO1 as pulled-up + //P2REN |= BIT1; // DIO1pull-up register enable + DIO1_DIR&=~DIO1_BIT; + DIO1_IES_L; // DIO1 Hi/Low edge + DIO1_IE_L; // DIO1 interrupt enabled + DIO1_IFG_L; // DIO1IFG cleared + + //DIO3ΪP2.3 + //P2DIR &= ~BIT3; + //P2OUT |= BIT3; // Configure DIO3 as pulled-up + //P2REN |= BIT3; // DIO3pull-up register enable + DIO3_DIR&=~DIO3_BIT; + DIO3_IES_L; // DIO3 Hi/Low edge + DIO3_IE_L; // DIO3 interrupt enabled + DIO3_IFG_L; // DIO3IFG cleared + + + //SX1276 SPI I/O definitions + // Configure SPI + //SPI SET + SPI_NSS_DIR_OUT; + SPI_NSS_OUT_1; // /CS disable + + // SPI option select + SPI_PSEL |= SPI_SI_BIT+SPI_SO_BIT+SPI_CLK_BIT; + + UCB0CTLW0 |= UCSWRST; // **Put state machine in reset** + UCB0CTLW0 |= UCMST|UCSYNC|UCCKPH|UCMSB; // 3-pin, 8-bit SPI master + // Clock polarity high, MSB + UCB0CTLW0 |= UCSSEL__SMCLK; // SMCLK + UCB0BR0 = 1; // /2,fBitClock = fBRCLK/(UCBRx+1). + UCB0BR1 = 0; // + UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** + + //SX1276 RESET I/O definitions + RST_PDIR |= RST_BIT; + RST_POUT |= RST_BIT; + +} + +//////////////////////////////////////////////////////////////////////////////// +// : ˯߳ʱʱ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void ON_Sleep_Timerout(void) +{ + + //Timer1_A3 setup + TA1R =0; //ʱ + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768; + TA0CTL |= TASSEL_1 | MC_1; //ʱʱ +} +//////////////////////////////////////////////////////////////////////////////// +// : ر˯߳ʱʱ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void OFF_Sleep_Timerout(void) +{ + //TA0R =0; //ʱ + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768; + TA0CTL = TASSEL_1 | MC_0; //رնʱ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF λ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Reset(void) +{ + RST_POUT &= ~RST_BIT; //ӲλIO0 + DelayMs(6); //ʱ + RST_POUT |= RST_BIT; //Ϊ1 + DelayMs(5); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ +// : uint8_t addr,Ĵַ uint8_t *buffer,ָ uint8_t sizeָ볤 +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +{ + uint8_t i; + SPI_PSEL |= SPI_SO_BIT;//SPIbugĹ쳣 + SPI_NSS_OUT_0; +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + UCB0IFG &= ~UCRXIFG; // Clear flag + UCB0TXBUF = (addr | 0x80); // Send address + while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish + UCB0IFG &= ~UCTXIFG; // Clear flag + for( i = 0; i < size; i++ ) + { + UCB0TXBUF = buffer[i]; // Send data + while (!(UCB0IFG&UCTXIFG)); // Wait for TX to finish + UCB0IFG &= ~UCTXIFG; + } +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + SPI_NSS_OUT_1; + SPI_PSEL &= ~SPI_SO_BIT;//SPIbugĹ쳣 +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ +// : uint8_t addr,Ĵַ uint8_t *buffer,洢ָ uint8_t sizeҪij +// ز : ݷص*buffer +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +{ + uint8_t i; + SPI_PSEL |= SPI_SO_BIT;//SPIbugĹ쳣 + SPI_NSS_OUT_0; +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + UCB0IFG &= ~UCRXIFG; // Clear flag + UCB0TXBUF = (addr & 0x7F); // Send address + while (!(UCB0IFG&UCTXIFG)); // Wait for end of addr byte TX + UCB0IFG &= ~UCTXIFG; // Clear flag + for( i = 0; i < size; i++ ) + { + UCB0TXBUF = 0; //Initiate next data RX + while (!(UCB0IFG&UCRXIFG)); // Wait for RX to finish + buffer[i] = UCB0RXBUF; // Store data from last data RX + //ȡUCB0RXBUFIFGԶReset + } +// _NOP();_NOP();_NOP();_NOP(); +// _NOP();_NOP();_NOP();_NOP(); + SPI_NSS_OUT_1; + SPI_PSEL &= ~SPI_SO_BIT;//SPIbugĹ쳣 + UCB0IFG=0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַд1ֽ +// : uint8_t addr,Ĵַ uint8_t data +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Write( uint8_t addr, uint8_t data ) +{ + SX1276WriteBuffer( addr, &data, 1 ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF Ĵַ1ֽ +// : uint8_t addr,Ĵַ uint8_t *dataݴ洢ַ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276Read( uint8_t addr, uint8_t *data ) +{ + SX1276ReadBuffer( addr, data, 1 ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF FIFOд +// : uint8_t *buffer,ָ uint8_t size +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteFifo( uint8_t *buffer, uint8_t size ) +{ + SX1276WriteBuffer( 0, buffer, size ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF FIFO +// : uint8_t *buffer,ָ uint8_t size +// ز : uint8_t *buffer 洢ȡ +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276ReadFifo( uint8_t *buffer, uint8_t size ) +{ + SX1276ReadBuffer( 0, buffer, size ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF TX/RXPAл +// : bool txEnable л߼ +// ز : +// ˵ :棺ΪTX٣ΪRX ΪӲPAIO +//////////////////////////////////////////////////////////////////////////////// +void SX1276WriteRxTx( bool txEnable ) +{ + if( txEnable != 0 ) //Ϊ棬ΪTX + { + ; + } + else //Ϊ٣ΪRX + { + ; + } +} + +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/RF-Module.c b/RF-AP/RF-Module.c new file mode 100644 index 0000000..2823370 --- /dev/null +++ b/RF-AP/RF-Module.c @@ -0,0 +1,491 @@ +// Haybin_Wu +// Shenitech-RD +// 2016.5 +// Built with IAR Embedded Workbench v6.2 +//****************************************************************************** +// Modify by Qian Xianghong +// 2020.10 +// ޸־ģɴںRF˫͸ģʽ +//****************************************************************************** +#include +#include +#include +#include +#include "FR2433-RFSX.h" +#include "RF_SX1276.h" + +// Ƶò +lora_param_t Lora_Param; + +#define TRAN_BUF_SIZE (1024) + +// UA1ӡ +char printBuf[200]; +void uart_print() +{ +#if 0 // ӡڵ2MD0MD1ģʽѡ + char *p = printBuf; + while(*p) + { + if(*p == '\n') // ǰӻس + { + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = '\r'; + } + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = *p++; + } +#endif +} + +// ɱĺ궨 +#define PRINTF(format, ...) \ +{ \ + snprintf(printBuf, sizeof(printBuf), format, ##__VA_ARGS__); \ + uart_print(); \ +} + +// UA0λݵbuf +uint8_t UA0_RxBuf[TRAN_BUF_SIZE] = {0}; +uint16_t UA0_RxBuf_Length = 0; +uint16_t UA0_RxBuf_offset = 0; +// UA0ճʱ +volatile uint8_t UA0_Rx_Timeout = 1; + +// RFݵbuf +uint8_t RF_RxBuf[TRAN_BUF_SIZE] = {0}; +uint16_t RF_RxBuf_Length = 0; +uint16_t RF_RxBuf_offset = 0; +// RFճʱ־ +volatile uint8_t RF_Rx_Timeout = 1; + +//////////////////////////////////////////////////////////////////////////////// +// ڳʼ +void UA0_Init(uint32_t baudrate) +{ + // Configure UART + UCA0CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + if(baudrate == 115200) + { + UCA0BR0 = 4; // 8000000/16/115200//λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.44444 + UCA0MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢Baud Rate + } + else if(baudrate == 38400) + { + UCA0BR0 = 13; // 8000000/16/38400 /λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.33333 + UCA0MCTLW = 0x8400 | UCOS16 | UCBRF_0;//΢Baud Rate + } + else + { + UCA0BR0 = 52; // 8000000/16/9600 /λ16 UCOS16λҪλ + UCA0BR1 = 0; // Fractional portion = 0.33333 + UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1;//΢Baud Rate + } + UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt +} + +// Ӧ +void UA0_Response(char *s) +{ + while(*s) + { + while(!(UCA0IFG & UCTXIFG)); + UCA0TXBUF = *s++; + } + // ȴͽ + while(!(UCA0IFG & UCTXCPTIFG)); + DelayMs(2); +} + +//////////////////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////////////////// + int main(void) +{ + uint8_t sendCh; + + WDTCTL = (WDTPW | WDTHOLD); // Stop WDT + // Port Configuration all un-used pins to output low + P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; + P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; + PM5CTL0 &= ~LOCKLPM5;//Ź + + // Configure DCO Clock + //ⲿʱԴ + P2SEL0 |= (BIT0 | BIT1); // set XT1 pin as second function + do + { + CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag + SFRIFG1 &= ~OFIFG; + } while (SFRIFG1 & OFIFG); // Test oscillator fault flag + //־ڽ͹ + + __bis_SR_register(SCG0); // disable FLL + CSCTL3 |= SELREF__XT1CLK; // ⲿ 32768hz reference source + CSCTL0 = 0; // clear DCO and MOD registers + CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first + CSCTL1 |= DCORSEL_3; //DCO=8Mhz + CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz + __delay_cycles(3); + __bic_SR_register(SCG0); // enable FLL + while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked + + CSCTL4 = SELREF__XT1CLK + SELMS__DCOCLKDIV;// set XT1CLK(32768Hz) as ACLK source & MCLK/SMCLK=DCO + + //Timer0_A0 setup + TA0CCTL0 = CCIE; // TACCR0 interrupt enabled + TA0CCR0 = 32768 / 32; // ڽճʱ: 1000/32=31.25ms + TA0CTL = MC__STOP | TACLR; // Stop mode, Clear counter + + //Timer1_A0 setup + TA1CCTL0 = CCIE; // TACCR0 interrupt enabled + TA1CCR0 = 32768 / 4; // RFճʱ: 1000/4=250ms + TA1CTL = MC__STOP | TACLR; // Stop mode, Clear counter + + // ģȱʡ + Lora_Param.sof = 0xC2; + Lora_Param.addr = 0xADF2; // ͨŵַ0xADF2 + Lora_Param.sf = 6; // sf=12 + Lora_Param.baud = 3; // 9600 + Lora_Param.cr = 0; // cr=4/5 + Lora_Param.ch = 9; // 479MHz + Lora_Param.power = 1; // 17dBm + Lora_Param.freqcast = 0; // freqcast off + Lora_Param.bw = 9; // 500kHz + Lora_Param.unicast = 0; // unicast off + + // Configure UART pins + P1SEL1 &= ~(BIT4 | BIT5); // set 2-UART pin as second function + P1SEL0 |= (BIT4 | BIT5); // set 2-UART pin as second function + if(Lora_Param.baud == 7) + UA0_Init(115200); + else if(Lora_Param.baud == 5) + UA0_Init(38400); + else + UA0_Init(9600); + +#if 0 // ôӡ + // Configure UART pins + P2SEL1 &= ~(BIT5 | BIT6); // set 2-UART pin as second function + P2SEL0 |= (BIT5 | BIT6); // set 2-UART pin as second function + // Configure UART + UCA1CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + UCA1BR0 = 4; // 8000000/16/115200//λ16 UCOS16λҪλ + UCA1BR1 = 0; // Fractional portion = 0.44444 + UCA1MCTLW = 0x5500 | UCOS16 | UCBRF_5;//΢Baud Rate + UCA1CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt + + // ӡλԭ(Դ𣬲Ź) + PRINTF("\nModule reseted: %04X\n", PMMIFG); + +#else // MD0MD1ģʽ + P2SEL1 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO + P2SEL0 &= ~(BIT3 | BIT5 | BIT6); // set 2-UART pin as GPIO + P2DIR &= ~(BIT5 | BIT6); // Input + P2REN |= (BIT5 | BIT6); // enable pull + P2OUT &= ~(BIT5 | BIT6); // pull-down + + P2DIR |= BIT3; // Output + P2OUT |= BIT3; // Output high +#endif + + _EINT(); + +#if 0 + // ӡλԭ(Դ𣬲Ź) + RF_RxBuf[0] = PMMIFG >> 8; + RF_RxBuf[1] = PMMIFG & 0xFF; + RF_RxBuf_Length = 2; + RF_RxBuf_offset = 0; + UCA0IE |= UCTXIE; + while(UCA0IE & UCTXIE); +#endif + // Ĵλԭ + SYSRSTIV; + + //ģʼ + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + // ʼڽģʽ + LSD_RF_RXmode(RF_PAYLOAD_LEN); + // ĬϷŵ + sendCh = Lora_Param.ch; + + // Ź: ʱʱΪ2^27/SMCLK8000000ƵԼΪ16s + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + while(1) + { +#if 1 + // TODO: ι + WDTCTL = (WDTPW | WDTCNTCL | WDTIS_1); + + // ģʽ + if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6)) + { + if(UA0_RxBuf_Length - UA0_RxBuf_offset >= sizeof(Lora_Param)) + { + if(UA0_RxBuf[UA0_RxBuf_offset] == 0xC2) + { + // + memmove(&Lora_Param, UA0_RxBuf + UA0_RxBuf_offset, sizeof(Lora_Param)); + // ߵַߵֽ + Lora_Param.addr = (Lora_Param.addr << 8) | (Lora_Param.addr >> 8); + + //ģʼ + uint8_t try_count = 3; //ʼ3 + while(try_count) + { + // б仯ģʼ + if(SX127x_initLora(&Lora_Param) == NORMAL) + break; + try_count--; + } + if(try_count == 0) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + + // Ĭϴڽģʽ + LSD_RF_RXmode(RF_PAYLOAD_LEN); + // ĬϷŵ + sendCh = Lora_Param.ch; + // Ӧ + UA0_Response("OK\r\n"); + + // ı䴮ڲ + if(Lora_Param.baud == 7) + UA0_Init(115200); + else if(Lora_Param.baud == 5) + UA0_Init(38400); + else + UA0_Init(9600); + } + + UA0_RxBuf_offset = UA0_RxBuf_Length; + } + } + // ͸ģʽ + else if((P2IN & (BIT5 | BIT6)) == 0) +#endif + { + if(UA0_RxBuf_Length > UA0_RxBuf_offset) + { + // 㴫䣬ָĿַŵ + if(Lora_Param.unicast) // 㷢 + { + if(UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 3) + sendCh = UA0_RxBuf[2]; + } + else if(Lora_Param.freqcast) // ָŵ + { + if(UA0_RxBuf_offset == 0 && UA0_RxBuf_Length > 1) + { + sendCh = UA0_RxBuf[0]; + UA0_RxBuf_offset = 1; // ͵1ֽ + } + } + + if(UA0_RxBuf_Length - UA0_RxBuf_offset >= RF_PAYLOAD_LEN) + { + LSD_RF_FreqSet(sendCh); + LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, RF_PAYLOAD_LEN); + UA0_RxBuf_offset += RF_PAYLOAD_LEN; + PRINTF("Send packet\n"); + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + + } + else if(UA0_Rx_Timeout) + { + LSD_RF_FreqSet(sendCh); + LSD_RF_SendPacket(UA0_RxBuf + UA0_RxBuf_offset, UA0_RxBuf_Length - UA0_RxBuf_offset); + UA0_RxBuf_offset = UA0_RxBuf_Length; + PRINTF("Send packet\n"); + + // лģʽ + LSD_RF_FreqSet(Lora_Param.ch); + LSD_RF_RXmode(RF_PAYLOAD_LEN); + } + } + } + + if(UA0_Rx_Timeout && UA0_RxBuf_offset == UA0_RxBuf_Length) + P2OUT |= BIT3; // Output high + } +} + +// Port 1 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=PORT1_VECTOR +__interrupt void Port_1(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(PORT1_VECTOR))) Port_1 (void) +#else +#error Compiler not supported! +#endif +{ + uint8_t offset = 0; + uint8_t len[1] = {0}; + uint8_t buf[RF_PAYLOAD_LEN]; + if(DIO0_IFG&DIO0_BIT) //ݴжϴ + { + // ж + DIO0_IFG &= ~DIO0_BIT; + + // ȡRF + LSD_RF_RxVariPacket(buf, len); //տɱݰΪʣֻýչ̶ݰ + + if(len[0] == 0) + return; + + TA1CTL = MC__STOP | TACLR; // ֹͣʱλ + TA1CTL = TASSEL__ACLK | MC__UP; // ¿ʼʱ + + offset = 0; + if(RF_Rx_Timeout) // µһݵ + { + RF_Rx_Timeout = 0; + + // λ + RF_RxBuf_Length = 0; + RF_RxBuf_offset = 0; + + if(Lora_Param.unicast) + { + // 㴫䣬ַŵУʧ + if(len[0] <= 3 || buf[2] != Lora_Param.ch || ((buf[0] << 8) | buf[1]) != Lora_Param.addr) + return; + // ǰ3ַ + offset = 3; + len[0] -= offset; + } + } + + PRINTF("Recv packet\n"); + + // ͸ģʽ + if((P2IN & (BIT5 | BIT6)) == 0) + { + if(RF_RxBuf_Length + len[0] <= TRAN_BUF_SIZE) + { + memmove(RF_RxBuf + RF_RxBuf_Length, buf + offset, len[0]); + // жϷʽ򴮿ת + RF_RxBuf_Length += len[0]; + UCA0IE |= UCTXIE; + } + } + } +} + +// Timer0 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER0_A0_VECTOR +__interrupt void Timer0_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) Timer0_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ֹͣʱλ + TA0CTL = MC__STOP | TACLR; + // ڽճʱ + UA0_Rx_Timeout = 1; +} + +// Timer1 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER1_A0_VECTOR +__interrupt void Timer1_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER1_A0_VECTOR))) Timer1_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ֹͣʱλ + TA1CTL = MC__STOP | TACLR; + // RFճʱ + RF_Rx_Timeout = 1; +} + +// UAR0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=USCI_A0_VECTOR +__interrupt void USCI_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + // ж + if((UCA0IE & UCRXIE) && (UCA0IFG & UCRXIFG)) + { + uint8_t c = UCA0RXBUF; + + TA0CTL = MC__STOP | TACLR; // ֹͣʱλ + TA0CTL = TASSEL__ACLK | MC__UP; // ¿ʼʱ + + if(UA0_Rx_Timeout) // µһݵ + { + UA0_Rx_Timeout = 0; + // λ + UA0_RxBuf_Length = 0; + UA0_RxBuf_offset = 0; + } + + if(UA0_RxBuf_Length < TRAN_BUF_SIZE) + { +#if 1 + // ģʽ + if((P2IN & (BIT5 | BIT6)) == (BIT5 | BIT6)) + { + // 1ַΪ0xC2 + if(UA0_RxBuf_Length > 0 || c == 0xC2) + UA0_RxBuf[UA0_RxBuf_Length++] = c; + } + // ͸ģʽ + else if((P2IN & (BIT5 | BIT6)) == 0) +#endif + { + // ͸ + UA0_RxBuf[UA0_RxBuf_Length++] = c; + } + + P2OUT &= ~BIT3; // Output low + } + } + + // ж + if((UCA0IE & UCTXIE) && (UCA0IFG & UCTXIFG)) + { + UCA0TXBUF = RF_RxBuf[RF_RxBuf_offset++]; // ַ + if(RF_RxBuf_offset >= RF_RxBuf_Length) // ȫ + { + // ֹж + UCA0IE &= ~UCTXIE; + } + } +} diff --git a/RF-AP/RF_SX1276.h b/RF-AP/RF_SX1276.h new file mode 100644 index 0000000..f868f29 --- /dev/null +++ b/RF-AP/RF_SX1276.h @@ -0,0 +1,1306 @@ +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: Haybin.Wu@studio +// ļ: +// 汾 V1.0 +// : IAR v6.20 +// : Haybin +// : 2016.05 +// : API +// ޸־ +//////////////////////////////////////////////////////////////////////////////// +// Modify by Qian Xianghong +// ޸־ +// 2020.10 +// 1. LSD_RF_SendPacket(): +// ޸жDIO0־ȷɣúʱ +// ǰ볤޸Ϊ8.Ĭֵмһ£ +// 2. LSD_RF_RXmode(): +// PayloadCrcErrorжϡ +// ǰ볤޸Ϊ8.Ĭֵмһ£ +// 3. LSD_RF_RxVariPacket(): +// жRxDonePayloadCRCErrorʶ +// ȶȡREG_LR_FIFORXCURRENTADDRĴֵٴӸõַʼȡݡ +// 4. LSD_RF_RxFixiPacket(): +// жRxDonePayloadCRCErrorʶ +// 5. SX127x_initLora()ڸسʼLoRa +// +//2021.05 +// 1. SX127x_initLora(): +// PayloadCrcУ顣 +// 2. LSD_RF_RxVariPacket(): +// жCrcǷá +// 3. LSD_RF_RxFixiPacket(): +// жCrcǷá +// +//////////////////////////////////////////////////////////////////////////////// +#include +#include +#include "FR2433-RFSX.h" +#ifndef RF_SX1276 +#define RF_SX1276 + +uint8_t LSD_RF_FreqSet(uint8_t ch); +uint8_t LSD_RF_PoutSet(uint8_t power); +//====================================================================================== +#define RF_PAYLOAD_LEN (64) + +#pragma pack(push, 1) +// LORAҫ +typedef struct +{ + uint8_t sof; // ǰ룬̶Ϊ0xC2 + uint16_t addr; // ͨŵַ + unsigned char sf : 3; // Ƶ: 0-1-7,...,6-12,7- + unsigned char baud : 3; // ڲʣ3-9600,7-115200, ౣ + unsigned char cr : 2; // : 0-4/5,1-4/6,2-4/7,3-4/8 + uint8_t ch; // ͨŵ: 0~40(470M~510M),ౣ + unsigned char power : 2; // Power: 0-20dBm,1-17dBm,2-14dBm,3-11dBm + unsigned char freqcast: 1; // Ƿָŵ + unsigned char bw : 4; // 0-7.8kHz,1-10.4kHz,...,9-500kHz, ౣ + unsigned char unicast : 1; // Ƿ񶨵㷢 +} lora_param_t; +#pragma pack(pop) +//====================================================================================== +/*! + * SX1276 LoRa General parameters definition + */ +typedef struct sLoRaSettings +{ + uint32_t RFFrequency; + int8_t Power; + uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz, + // 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved] + uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips] + uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + bool CrcOn; // [0: OFF, 1: ON] + bool ImplicitHeaderOn; // [0: OFF, 1: ON] + bool RxSingleOn; // [0: Continuous, 1 Single] + bool FreqHopOn; // [0: OFF, 1: ON] + uint8_t HopPeriod; // Hops every frequency hopping period symbols + uint32_t TxPacketTimeout; + uint32_t RxPacketTimeout; + uint8_t PayloadLength; +}tLoRaSettings; + +/*! + * RF packet definition + */ +#define RF_BUFFER_SIZE_MAX 128 +#define RF_BUFFER_SIZE 80 + +/*! + * RF state machine + */ +//LoRa +typedef enum +{ + RFLR_STATE_IDLE, + RFLR_STATE_RX_INIT, + RFLR_STATE_RX_RUNNING, + RFLR_STATE_RX_DONE, + RFLR_STATE_RX_TIMEOUT, + RFLR_STATE_TX_INIT, + RFLR_STATE_TX_RUNNING, + RFLR_STATE_TX_DONE, + RFLR_STATE_TX_TIMEOUT, + RFLR_STATE_CAD_INIT, + RFLR_STATE_CAD_RUNNING, +}tRFLRStates; + +/*! + * SX1276 definitions + */ +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +/*! + * SX1276 Internal registers Address + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +//#define REG_LR_BANDSETTING 0x04 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_NBRXBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 + +/*! + * SX1276 LoRa bit control definition + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegBandSetting + */ +#define RFLR_BANDSETTING_MASK 0x3F +#define RFLR_BANDSETTING_AUTO 0x00 // Default +#define RFLR_BANDSETTING_DIV_BY_1 0x40 +#define RFLR_BANDSETTING_DIV_BY_2 0x80 +#define RFLR_BANDSETTING_DIV_BY_6 0xC0 + + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RFLR_LNA_BOOST_LF_GAIN 0x08 +#define RFLR_LNA_BOOST_LF_IP3 0x10 +#define RFLR_LNA_BOOST_LF_BOOST 0x18 +#define RFLR_LNA_RXBANDFORCE_MASK 0xFB +#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + + + +/*! + * RegFifoRxNbBytes (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueMsb (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueLsb (Read Only) // + */ + + +/*! + * RegRxPacketCntValueMsb (Read Only) // + */ + + + /*! + * RegRxPacketCntValueLsb (Read Only) // + */ + + + /*! + * RegModemStat (Read Only) // + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) // + */ + + + /*! + * RegPktRssiValue (Read Only) // + */ + + +/*! + * RegRssiValue (Read Only) // + */ + + + /*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F + +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + + /*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + + +/*! + * RegHopChannel (Read Only) + */ + +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40 +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegModemConfig3 + */ +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +/*! + * RegFormerTemp + */ + +typedef struct sSX1276LR +{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + + uint8_t RegTestReserved02[0x06 - 0x02]; // 0x02-0x05 + // uint8_t RegRes02; // 0x02 + // uint8_t RegRes03; // 0x03 + // uint8_t RegBandSetting; // 0x04 + // uint8_t RegRes05; // 0x05 + + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + // LoRa registers + uint8_t RegFifoAddrPtr; // 0x0D + uint8_t RegFifoTxBaseAddr; // 0x0E + uint8_t RegFifoRxBaseAddr; // 0x0F + uint8_t RegFifoRxCurrentAddr; // 0x10 + uint8_t RegIrqFlagsMask; // 0x11 + uint8_t RegIrqFlags; // 0x12 + uint8_t RegNbRxBytes; // 0x13 + uint8_t RegRxHeaderCntValueMsb; // 0x14 + uint8_t RegRxHeaderCntValueLsb; // 0x15 + uint8_t RegRxPacketCntValueMsb; // 0x16 + uint8_t RegRxPacketCntValueLsb; // 0x17 + uint8_t RegModemStat; // 0x18 + uint8_t RegPktSnrValue; // 0x19 + uint8_t RegPktRssiValue; // 0x1A + uint8_t RegRssiValue; // 0x1B + uint8_t RegHopChannel; // 0x1C + uint8_t RegModemConfig1; // 0x1D + uint8_t RegModemConfig2; // 0x1E + uint8_t RegSymbTimeoutLsb; // 0x1F + uint8_t RegPreambleMsb; // 0x20 + uint8_t RegPreambleLsb; // 0x21 + uint8_t RegPayloadLength; // 0x22 + uint8_t RegMaxPayloadLength; // 0x23 + uint8_t RegHopPeriod; // 0x24 + uint8_t RegFifoRxByteAddr; // 0x25 + uint8_t RegModemConfig3; // 0x26 + uint8_t RegTestReserved27[0x31 - 0x27]; // 0x27-0x30 + //void SX1276LoRaSetNbTrigPeaks( uint8_t value )õ + uint8_t RegTestReserved31; // 0x31 + uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x3F + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + + uint8_t RegTestReserved43[0x4B - 0x43]; // 0x43-0x4A + uint8_t RegTcxo; // 0x4B + uint8_t RegTestReserved4C; // 0x4C + uint8_t RegPaDac; // 0x4D + uint8_t RegTestReserved4E[0x5B - 0x4E]; // 0x4E-0x5A + uint8_t RegFormerTemp; // 0x5B + uint8_t RegTestReserved5C[0x61 - 0x5C]; // 0x5C-0x60 + // Additional settings + uint8_t RegAgcRef; // 0x61 + uint8_t RegAgcThresh1; // 0x62 + uint8_t RegAgcThresh2; // 0x63 + uint8_t RegAgcThresh3; // 0x64 + uint8_t RegTestReserved65[0x70 - 0x65]; // 0x65-0x6F + uint8_t RegPll; // 0x70 +}tSX1276LR; +////////////////////////////////////////////////////////////////////////////// +typedef enum +{ + Init_LoRa_0_8K, + Init_LoRa_4_8K, + Init_LoRa_10k, +}tSX127xInitPara; //ö + +typedef enum +{ + NORMAL, // + PARAMETER_INVALID, // + SPI_READCHECK_WRONG, //SPI +}tSX127xError; //ö + +typedef enum +{ + SLEEP, + STANDBY, + TX_ONGOING, + RX_ONGOING, +}tSX127xState; //RF״̬ûԲʹ + +typedef enum +{ + HOLDON, + TX, + LISTENING, +}tRadio_Machine; //߼״̬ûԲʹ + +typedef enum +{ + MASTER, + SLAVE, +}tMasterSlave; //ö ʱ + +typedef struct +{ + tMasterSlave MasterSlave; // + tSX127xState SX127xState; //״̬ + tRadio_Machine Machine; //߼״̬ +}stRadio_Situation; //״̬ṹ + +const unsigned char Freq_Cal_Tab[]= +{ + 0x75,0x80,0x00,//470MHz + 0x75,0xC0,0x00,//471MHz + 0x76,0x00,0x00,//472MHz + 0x76,0x40,0x00,//473MHz + 0x76,0x80,0x00,//474MHz + 0x76,0xC0,0x00,//475MHz + 0x77,0x00,0x00,//476MHz + 0x77,0x40,0x00,//477MHz + 0x77,0x80,0x00,//478MHz + 0x77,0xC0,0x00,//479MHz + 0x78,0x00,0x00,//480MHz + 0x78,0x40,0x00,//481MHz + 0x78,0x80,0x00,//482MHz + 0x78,0xC0,0x00,//483MHz + 0x79,0x00,0x00,//484MHz + 0x79,0x40,0x00,//485MHz + 0x79,0x80,0x00,//486MHz + 0x79,0xC0,0x00,//487MHz + 0x7A,0x00,0x00,//488MHz + 0x7A,0x40,0x00,//489MHz + 0x7A,0x80,0x00,//490MHz + 0x7A,0xC0,0x00,//491MHz + 0x7B,0x00,0x00,//492MHz + 0x7B,0x40,0x00,//493MHz + 0x7B,0x80,0x00,//494MHz + 0x7B,0xC0,0x00,//495MHz + 0x7C,0x00,0x00,//496MHz + 0x7C,0x40,0x00,//497MHz + 0x7C,0x80,0x00,//498MHz + 0x7C,0xC0,0x00,//499MHz + 0x7D,0x00,0x00,//500MHz + 0x7D,0x40,0x00,//501MHz + 0x7D,0x80,0x00,//502MHz + 0x7D,0xC0,0x00,//503MHz + 0x7E,0x00,0x00,//504MHz + 0x7E,0x40,0x00,//505MHz + 0x7E,0x80,0x00,//506MHz + 0x7E,0xC0,0x00,//507MHz + 0x7F,0x00,0x00,//508MHz + 0x7F,0x40,0x00,//509MHz + 0x7F,0x80,0x00,//510MHz +}; + +//extern stRadio_Situation SX127xSituation; +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : tSX127xInitPara initPara Init_LoRa_0_8K, Init_LoRa_4_8K , Init_LoRa_10k, +// ز : tSX127xError ö +// ˵ : ʼʱŵʼĬΪ0ŵ +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_init(tSX127xInitPara initPara) +{ + uint8_t test = 0; + if(initPara>Init_LoRa_10k) // + { + return PARAMETER_INVALID; // + } + SX1276Init_IO(); // PAIOڳʼ + SX1276Reset(); //λRF + //init Regs + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PACONFIG, 0xff ); + SX1276Write( REG_LR_PADAC, RFLR_PADAC_20DBM_ON ); + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US); + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA); + SX1276Write( REG_LR_PAYLOADLENGTH,2); + SX1276Write( REG_LR_MODEMCONFIG3,\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON| + RFLR_MODEMCONFIG3_AGCAUTO_ON); + //BW,SF,CR,Header,CRC +// SX1276Write( REG_LR_MODEMCONFIG2,0xFF); +// SX1276Write( REG_LR_SYMBTIMEOUTLSB,0xFF); + switch(initPara){ + case Init_LoRa_0_8K: +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON| +// RFLR_MODEMCONFIG3_AGCAUTO_ON); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_125_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_9|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); + SX1276Write( REG_LR_PREAMBLELSB,10); + SX1276Write(0x31,0x55); + SX1276Read( 0x31,&test); + break; + case Init_LoRa_4_8K: +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF| +// RFLR_MODEMCONFIG3_AGCAUTO_OFF); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_8|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); +// SX1276Write( REG_LR_PREAMBLEMSB,1); + SX1276Write( REG_LR_PREAMBLELSB,10); + break; + case Init_LoRa_10k: + SX1276Read( 0x31,&test); + SX1276Write( 0x31,(test& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); +// SX1276Write( REG_LR_MODEMCONFIG3,\ +// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF| +// RFLR_MODEMCONFIG3_AGCAUTO_ON); + + SX1276Write( REG_LR_MODEMCONFIG1,\ + RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\ + RFLR_MODEMCONFIG1_IMPLICITHEADER_ON); + SX1276Write( REG_LR_MODEMCONFIG2,\ + RFLR_MODEMCONFIG2_SF_6|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON); +// SX1276Write( REG_LR_PREAMBLEMSB,4); + SX1276Write( REG_LR_PREAMBLELSB,10); + break; + default: + break; + } + if(!LSD_RF_FreqSet(1)) //Ϊ0ŵ + return SPI_READCHECK_WRONG; + + return NORMAL; +} + +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : lora_param_t lora +// ز : tSX127xError ö +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_initLora(lora_param_t *lora) +{ + static uint8_t first = 1; + + // + if(lora->sof != 0xC2 || lora->sf > 6 || (lora->baud != 3 && lora->baud != 5 && lora->baud != 7) || lora->ch > 40 || lora->bw > 9) + return PARAMETER_INVALID; + + if(first) + { + first = 0; + SX1276Init_IO(); // PAIOڳʼ + } + SX1276Reset(); //λRF + + //лLoRamodestandby״̬ + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + + /*------------------------------------------------ + SPI ֤ */ + uint8_t test = 0; + SX1276Write( REG_LR_HOPPERIOD,0x91 );//ѡһòļĴ֤ + SX1276Read( REG_LR_HOPPERIOD,&test); + if(test!=0x91) + return SPI_READCHECK_WRONG; + + SX1276Write( REG_LR_PACONFIG, 0xff ); + + //Frequency Configuration + LSD_RF_FreqSet(lora->ch); //Ƶ + //PA Configuration + switch(lora->power) + { + case 0: // 20dBm + LSD_RF_PoutSet(15); + break; + case 1: // 17dBm + LSD_RF_PoutSet(15); + break; + case 2: // 14dBm + LSD_RF_PoutSet(12); + break; + case 3: // 11dBm + LSD_RF_PoutSet(9); + break; + } + + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US); + // PA Rampʱ䣬ûLDOܿʵPA Rampʱ + // Rampʱ̳LDOʱֽTXϵͳΪRFźŲֵ + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);//ر Over Current Protection + + //PayloadLength ʼ + SX1276Write( REG_LR_PAYLOADLENGTH, RF_PAYLOAD_LEN); + //ע⣬ͷģʽImplicit Headerʱǰ涨շ˫PL + + //BWCRImplictHeader_On (SF6) / Off (SF7~12) + SX1276Write( REG_LR_MODEMCONFIG1,\ + (((uint8_t)(lora->bw << 4)) | ((uint8_t) ((lora->cr + 1) << 1))) | (lora->sf == 0 ? 0x01 : 0x00)); + + //SFPayloadCrc_On + SX1276Write( REG_LR_MODEMCONFIG2,\ + ((uint8_t)((lora->sf + 6) << 4)) | 0x04); + + uint8_t temp = 0; + SX1276Read( 0x31,&temp); + if(0 == lora->sf) //SF = 6Ҫú + { + SX1276Write( 0x31,(temp& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); + } + else + { + SX1276Write( 0x31,(temp& 0xF8)|0x03); + SX1276Write( 0x37,0x0A); + } + + //ŻǷAutoAGCĬϿ + // SF12500kHz£뿪ʺܸ + SX1276Write( REG_LR_MODEMCONFIG3,(\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON\ + )|RFLR_MODEMCONFIG3_AGCAUTO_ON); + + // Ƶѡ + SX1276Write( REG_LR_DIOMAPPING2, RFLR_DIOMAPPING2_DIO4_01); + + return NORMAL; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : Ϊǣ preambleĻĬֵ +//////////////////////////////////////////////////////////////////////////////// +void SX1276_TxPacket(uint8_t*data,uint8_t size) +{ + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,8); + SX1276Write( REG_LR_PAYLOADLENGTH,size); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,data,size); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE_MASK)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : uint8_t clen ɱݰ´ֵЧ̶ݰΪֵ +// ز : +// ˵ : պpreambleûĬֵΪ +//////////////////////////////////////////////////////////////////////////////// +void Rx_mode(uint8_t clen) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,8); + SX1276Write( REG_LR_PAYLOADLENGTH,clen); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE_MASK | RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFտɱݰ +// : uint8_t*cbufָ,uint8_t *csizeسָ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxVariPacket(uint8_t*cbuf,uint8_t *csize) +{ + uint8_t flag, hop, ptr; + + SX1276Read(REG_LR_IRQFLAGS, &flag); + SX1276Read(REG_LR_HOPCHANNEL, &hop); + + SX1276Read(REG_LR_FIFORXCURRENTADDR, &ptr); + SX1276Read(REG_LR_NBRXBYTES,csize); + SX1276Write( REG_LR_FIFOADDRPTR,ptr); + SX1276ReadFifo(cbuf,*csize); + + SX1276Write(REG_LR_IRQFLAGS,0xff); + if(!(flag & RFLR_IRQFLAGS_RXDONE) || ((hop & RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON) && (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR))) + *csize = 0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RFչ̶ݰ +// : uint8_t*cbufָ,uint8_t csizeչ̶ +// ز : +// ˵ : 10kʱֻܲù̶ݰ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxFixiPacket(uint8_t*cbuf,uint8_t *csize) +{ + uint8_t flag, hop; + + SX1276Read(REG_LR_IRQFLAGS, &flag); + SX1276Read(REG_LR_HOPCHANNEL, &hop); + + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276ReadFifo(cbuf,*csize); + + SX1276Write(REG_LR_IRQFLAGS,0xff); + if(!(flag & RFLR_IRQFLAGS_RXDONE) || ((hop & RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON) && (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR))) + *csize = 0; +} +//////////////////////////////////////////////////////////////////////////////// +// : RFstandby״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_StandbyMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF벻ͬŵ +// : uint8_t ch Χ0-40 +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +uint8_t LSD_RF_FreqSet(uint8_t ch) +{ + uint8_t test_FRFMSB = 0,test_FRFMID=0,test_FRFLSB=0; +#if 0 + SX1276Write( REG_LR_FRFMSB,Freq_Cal_Tab[3*ch]); + SX1276Write( REG_LR_FRFMID,Freq_Cal_Tab[3*ch+1]); + SX1276Write( REG_LR_FRFLSB,Freq_Cal_Tab[3*ch+2]); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB !=Freq_Cal_Tab[3*ch]) + return 0; + if(test_FRFMID !=Freq_Cal_Tab[3*ch+1]) + return 0; + if(test_FRFLSB !=Freq_Cal_Tab[3*ch+2]) + return 0; +#else + const uint32_t FXOSC = 32000000ul; + float fstep = FXOSC / 524288.0; + uint32_t freq = 470000000ul + ch * 1000000ul; + uint32_t frf = (uint32_t) (freq / fstep + 0.5); + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_FRFMSB, (frf >> 16) & 0xFF); + SX1276Write( REG_LR_FRFMID, (frf >> 8) & 0xFF); + SX1276Write( REG_LR_FRFLSB, (frf & 0xff)); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB != ((frf >> 16) & 0xFF)) + return 0; + if(test_FRFMID != ((frf >> 8) & 0xFF)) + return 0; + if(test_FRFLSB != (frf & 0xff)) + return 0; +#endif + + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFù +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +uint8_t LSD_RF_PoutSet(uint8_t power) +{ + LSD_RF_StandbyMode(); + SX1276Write( REG_LR_PACONFIG, 0xf0|power); + uint8_t test = 0; + SX1276Read(REG_LR_PACONFIG,&test); + if((0xf0|power)!=test) + return 0; + SX1276Write( REG_LR_PADAC, 0x80|RFLR_PADAC_20DBM_ON ); + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : ݷɺDIO0ӵ͵ƽɸߵƽÿεô˺ԶȽDIO0Ϊͣȴߵƽ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SendPacket(uint8_t*cbuf,uint8_t csize) +{ + unsigned long int j=0xFFFFFF; //ʱãûҪʵ + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_L; //ֹDIO0ж + SX1276_TxPacket(cbuf,csize); // + while((!(DIO0_IFG&DIO0_BIT))&&j)j--; //ȴGDIO0ƽΪ + DIO0_IFG_L; //жϱ־λ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : uint8_t cclen ɱݰЧ̶ݰʱΪֵ +// ز : +// ˵ : ɺDIO0ӵ͵ƽɸߵƽ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RXmode(uint8_t cclen) +{ + Rx_mode(cclen); //RFջлRXģʽ + //SX_DIO0_DIR = 0; // + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_H; //ʹDIO0ж +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFSleep״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SleepMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + //P1OUT &= ~BIT4; //PA_TX ʼΪ0 + //P1OUT &= ~BIT5; //PA_TX ʼΪ0 Ŀǽʹ +} +//////////////////////////////////////////////////////////////////////////////// +// : RF CADʼ +// : +// ز : +// ˵ : DIO1--CADDetected DIO3---CADDone +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_CADinit(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0xf0); + SX1276Write( REG_LR_PREAMBLELSB,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK,\ + ~(RFLR_IRQFLAGS_CADDONE|RFLR_IRQFLAGS_CADDETECTED)); + // + SX1276Write( REG_LR_DIOMAPPING1,\ + RFLR_DIOMAPPING1_DIO3_00 | RFLR_DIOMAPPING1_DIO1_10); + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write(REG_LR_IRQFLAGS,0xff); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFCADŵһ +// : +// ز : +// ˵ : ʱԼΪ(2^SF+32)/BW +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_CAD_Sample(void) +{ + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_CAD ); +} +//////////////////////////////////////////////////////////////////////////////// +// : WORʼ +// : +// ز : +// ˵ : DIO1 :ж DIO3CADʱжϣҲΪǽռжϣ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WORInit(void) +{ + LSD_RF_CADinit(); //CADܳʼ + //CADDoneʹ + //SX_DIO3_DIR=0; // + DIO3_IFG_L; //DIO3־λ + DIO3_IES_L; //DIO3شʽ + DIO3_IE_H; //DIO3ж + //CADDetectedʹ + //SX_DIO1_DIR=0; // + DIO1_IFG_L; //DIO1־λ + DIO1_IES_L; //DIO1شʽ + DIO1_IE_H; //ʹDIO1ж + //رDIO0жʹ + DIO0_IE_L; //ʹDIO0ж +} +//////////////////////////////////////////////////////////////////////////////// +// : ִWOR +// : uint8_t cclen 0˯ߡ1CADģʽ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WOR_Execute(uint8_t cclen) +{ + switch(cclen) + { + case 0: //˯ + LSD_RF_SleepMode(); //˯ģʽ + ON_Sleep_Timerout(); //˯߳ʱʱ + break; + case 1: //CADģʽ + OFF_Sleep_Timerout(); //ر˯߳ʱʱ + LSD_RF_CAD_Sample(); //CADһ + + break; + default: break; + } +} +//////////////////////////////////////////////////////////////////////////////// +// : WORRX +// : +// ز : +// ˵ : ˳WORRXģʽǰpreambleȻֵ +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_WOR_Exit(uint8_t cclen) +{ + OFF_Sleep_Timerout(); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PAYLOADLENGTH,cclen); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); //set RF switch to RX path + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); + //SX_DIO0_DIR = 0; // + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_H; //ʹDIO0ж + + DIO1_IE_L; //ֹDIO1 + DIO3_IE_L; //ֹDIO3 + +} + +//////////////////////////////////////////////////////////////////////////////// +// : RFͻѰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_Awake(uint8_t*cbuf,uint8_t csize) +{ + //SX_DIO0_DIR = 0; + DIO0_IFG_L; //DIO0־λ + DIO0_IES_L; //DIO0شʽ + DIO0_IE_L; //ֹDIO0ж + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PAYLOADLENGTH,csize); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,cbuf,csize); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_PREAMBLEMSB,0x03);//set preamble length + SX1276Write( REG_LR_PREAMBLELSB,0xEC);//set preamble length + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); + while((!DIO0_IFG)); //ȴGDIO0ƽΪ + + DIO0_IFG_L; //жϱ־λ + //껽ݰ󣬽ǰʱĻĬֵ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0);//set preamble length + SX1276Write( REG_LR_PREAMBLELSB,10);//set preamble length + +} + +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/Wuhabin/RF-AP-RX.c b/RF-AP/Wuhabin/RF-AP-RX.c new file mode 100644 index 0000000..8f599fa --- /dev/null +++ b/RF-AP/Wuhabin/RF-AP-RX.c @@ -0,0 +1,388 @@ +// Haybin_Wu +// Shenitech-RD +// 2016.5 +// Built with IAR Embedded Workbench v6.2 +//****************************************************************************** +#include +#include +#include "FR2433-RFSX.h" +#include "RF_SX1276.h" + +uint32_t t=0; +void FRAM_Write (uint16_t FRAM_START,uint8_t *(Array),uint8_t Array_Long); +void FRAM_Read (uint16_t FRAM_START,uint8_t *(Array),uint8_t Array_Long); +void Set_DT(void); +void Refresh_Date(void); +void UART0_Tx(uint8_t data); + +#define FRAM_Date_START 0x1800 //Date 洢ʼַ +#define FRAM_ID_START 0x1806 //ID 洢ʼַ +#define RTC_Data 1920 //RTCʱ RTC_Data/32=s + +uint8_t Rx_Buf[64]; +uint8_t RF_RxBuf[64]; +uint8_t RF_RxBuf_size[1]; +uint8_t Rx_Data=0; +uint8_t Date_Time[6]= +{ + 30,//0 + 16,//1 + 10,//2ʱ + 22,//3 + 05,//4 + 16,//5 +}; +uint8_t Device_ID[4]={0xA6,0x52,0x40,0x01,};//豸ID + + //UART + void UART0_Tx(uint8_t data) + { + UCA0TXBUF = data; + while((UCTXIFG&UCA0IFG)==0); + UCA0IFG&=~UCTXIFG; + } + void Refresh_Date(void) + { + FRAM_Read(FRAM_Date_START,Date_Time,6); + Date_Time[0]=RTCCNT/32; + } + +//////////////////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////////////////// + int main(void) +{ + WDTCTL = WDTPW | WDTHOLD; // Stop WDT + // Port Configuration all un-used pins to output low + P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; + P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; + PM5CTL0 &= ~LOCKLPM5;//Ź + + // Configure DCO Clock +//ⲿʱԴ + P2SEL0 |= BIT0 | BIT1; // set XT1 pin as second function + do + { + CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag + SFRIFG1 &= ~OFIFG; + } while (SFRIFG1 & OFIFG); // Test oscillator fault flag + //־ڽ͹ + + __bis_SR_register(SCG0); // disable FLL + CSCTL3 |= SELREF__XT1CLK; // ⲿ 32768hz reference source + CSCTL0 = 0; // clear DCO and MOD registers + CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first + CSCTL1 |= DCORSEL_3; //DCO=8Mhz + CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz + __delay_cycles(3); + __bic_SR_register(SCG0); // enable FLL + while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked + + CSCTL4 = SELREF__XT1CLK + SELMS__DCOCLKDIV;// set XT1CLK(32768Hz) as ACLK source & MCLK/SMCLK=DCO + + + + + //Timer0_A3 setup + TA0CCTL0 = CCIE; // TACCR0 interrupt enabled + TA0CCR0 = 32768; + TA0CTL = TASSEL_1 | MC_1; // ACLK, continuous mode + + // Initialize RTC + RTCMOD = RTC_Data; + RTCCTL = (RTCSS__XT1CLK + RTCPS__1024 + RTCIE);//+ RTCSR// Source = 32kHz crystal, divided by 1024 + if(RTCCNT>RTC_Data){RTCCTL |= RTCSR;WDTCTL=0;} + Refresh_Date();//λˢʱ + //FRCTL0 = FRCTLPW | NWAITS_1;//FRRAM + FRAM_Read(FRAM_ID_START,Device_ID,4);//ˢ豸ID + + + // Configure UART pins + P1SEL0 |= BIT4 | BIT5; // set 2-UART pin as second function + // Configure UART + UCA0CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + UCA0BR0 = 52; // 8000000/8/9600//λ16 UCOS16λҪλ + UCA0BR1 = 0x00; // Fractional portion = 0.083 + //UCA0MCTLW = 0x11;//΢Baud Rate + UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1;//΢Baud Rate + UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt + + _EINT(); + + //ģԻ + uint8_t RF_error_flag=0; + for(uint8_t i=0;i<5;i++)//ʼ3 + { + if(SX127x_init(Init_LoRa_0_8K)==NORMAL) break; //ģʼʧܸλ + else RF_error_flag=1; + } + if(RF_error_flag==1) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + LSD_RF_RXmode(64); + //LSD_RF_SleepMode();//˯1.2uA + + + __bis_SR_register(LPM3_bits | GIE); // Enter LPM3 + //uint32_t i=0; + __no_operation(); // For debugger + + while(1) + { + //for(uint8_t i=0;i<64;i++)Rx_Buf[i-1]=i; + //LSD_RF_SendPacket(Rx_Buf,64); //64ֽݲ + //P3OUT ^= 0xC0; // Toggle P3.6,7 (LED) every 1s + //UART0_Tx(0xE5); + //if(SX127x_init(Init_LoRa_0_8K)==NORMAL); + //LSD_RF_SleepMode(); + LSD_RF_RXmode(64); + __bis_SR_register(LPM3_bits | GIE); // Enter LPM3 + } +} + + +// Port 1 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=PORT1_VECTOR +__interrupt void Port_1(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(PORT1_VECTOR))) Port_1 (void) +#else +#error Compiler not supported! +#endif +{ + if(DIO0_IFG&DIO0_BIT) //ݴжϴ + { + LSD_RF_RxVariPacket(RF_RxBuf,RF_RxBuf_size); //տɱݰΪʣֻýչ̶ݰ + DelayMs(10); + /*****************************************ָ************************/ + //if((RF_RxBuf[0]==0x01)&&(RF_RxBuf[1]==0x02))//(RF_rxBuf_size==(RF_RxBuf[3]+6)) + {//жָǷЧ + for(uint8_t i=0;i5) + { + t=0;//WDTCTL=0; + //LSD_RF_RxVariPacket(Rxbuffer,Rxbuffer_size); //տɱݰΪʣֻýչ̶ݰ + //LSD_RF_RXmode(30); //ÿηһݺ󣬽״̬ȴBģӦ + __bic_SR_register_on_exit(LPM3_bits); // Exit LPM3 + } +} +// Timer1 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER1_A0_VECTOR +__interrupt void Timer1_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER1_A0_VECTOR))) Timer1_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + ; + //if(t>5)WDTCTL=0;//P3OUT ^= 0xC0; +} + +// RTC interrupt service routine //һһ +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=RTC_VECTOR +__interrupt void RTC_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(RTC_VECTOR))) RTC_ISR (void) +#else +#error Compiler not supported! +#endif +{ + if(RTCIV&0x02) + { + Date_Time[0]=60; + Set_DT();// + FRAM_Write (FRAM_Date_START,Date_Time,6);//д + } +} + +// UAR0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=USCI_A0_VECTOR +__interrupt void USCI_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + uint8_t CS=0; + if((UCA0IV&USCI_UART_UCRXIFG)==USCI_UART_UCRXIFG) + { + Rx_Buf[Rx_Data++] = UCA0RXBUF; + //UCA0IFG&=~UCRXIFG; + } + if(Rx_Data>=10) + { + for(uint8_t i=0;i<(Rx_Buf[3]+1);i++) + CS+=Rx_Buf[i+2]; + if((Rx_Buf[0]==0x4D)&&(Rx_Buf[1]==0x4B)&&(Rx_Buf[Rx_Data-2]==0x55)&&(Rx_Buf[Rx_Data-1]==0x16)) + { + FRAM_Read(FRAM_ID_START,Device_ID,4);//ˢ豸ID + //01 ID//4D 4B 01 08 00 00 00 00 ID ID ID ID CS 16 + if((Rx_Buf[2]==0x01)&&(Rx_Buf[4]==Device_ID[0])&&(Rx_Buf[5]==Device_ID[1])&&(Rx_Buf[6]==Device_ID[2])&&(Rx_Buf[7]==Device_ID[3])) + { + Device_ID[0]=Rx_Buf[8];Device_ID[1]=Rx_Buf[9];Device_ID[2]=Rx_Buf[10];Device_ID[3]=Rx_Buf[11]; + FRAM_Write(FRAM_ID_START,Device_ID,4); + //FRAM_Read(FRAM_ID_START,Device_ID,4);//ˢ豸ID + UART0_Tx(0xE5); + Rx_Data=0; + } + //06 豸RTC//4D 4B 06 04 00 00 00 00 CS 16 + if((Rx_Buf[2]==0x06)&&(Rx_Buf[4]==Device_ID[0])&&(Rx_Buf[5]==Device_ID[1])&&(Rx_Buf[6]==Device_ID[2])&&(Rx_Buf[7]==Device_ID[3])) + { + Refresh_Date();//refresh time + //Return 4D 4B 06 A0 ID ID ID ID DT DT DT DT DT DT E5 16 + UART0_Tx(0x4D);UART0_Tx(0x4B);UART0_Tx(0x06);UART0_Tx(0xA0);UART0_Tx(Device_ID[0]);UART0_Tx(Device_ID[1]);UART0_Tx(Device_ID[2]);UART0_Tx(Device_ID[3]); + UART0_Tx(Date_Time[0]);UART0_Tx(Date_Time[1]);UART0_Tx(Date_Time[2]);UART0_Tx(Date_Time[3]);UART0_Tx(Date_Time[4]);UART0_Tx(Date_Time[5]); + UART0_Tx(0xE5);UART0_Tx(0x16); + Rx_Data=0; + } + //07 ͬRTC//4D 4B 06 04 00 00 00 00 CS 16 + if((Rx_Buf[2]==0x07)&&(Rx_Buf[4]==Device_ID[0])&&(Rx_Buf[5]==Device_ID[1])&&(Rx_Buf[6]==Device_ID[2])&&(Rx_Buf[7]==Device_ID[3])) + { + ; + } + } + } +} + + +// +void Set_DT(void) +{ + + if(Date_Time[0]>59)//λ + { + Date_Time[1]++; + Date_Time[0]=0; + } + if(Date_Time[1]>59)//ֽλ + { + Date_Time[2]++; + Date_Time[1]=0; + } + if(Date_Time[2]>23)//Сʱλ + { + Date_Time[3]++; + Date_Time[2]=0; + } +//31 +if((Date_Time[4]==1)||(Date_Time[4]==3)||(Date_Time[4]==5)||(Date_Time[4]==7)||(Date_Time[4]==8)||(Date_Time[4]==10)||(Date_Time[4]==12)) +{ + if(Date_Time[3]>31) + { + Date_Time[3]=1; + Date_Time[4]++; + } + if(Date_Time[4]>12) + { + Date_Time[4]=1; + Date_Time[5]++; + } + if(Date_Time[5]>99)Date_Time[5]=0; +} +//30 +if((Date_Time[4]==4)||(Date_Time[4]==6)||(Date_Time[4]==9)||(Date_Time[4]==11)) +{ + if(Date_Time[3]>30) + { + Date_Time[3]=1; + Date_Time[4]++; + } +} +//2 +if(Date_Time[4]==2) +{ + if((Date_Time[5]%4==0&&Date_Time[5]%100!=0) ||(Date_Time[5]%400==0))// + { + if(Date_Time[3]>29) + { + Date_Time[3]=1; + Date_Time[4]++; + } + } + else + { + if(Date_Time[3]>28) + { + Date_Time[3]=1; + Date_Time[4]++; + } + } + } +} + +void FRAM_Write (uint16_t FRAM_START,uint8_t *(Array),uint8_t Array_Long) +{ + SYSCFG0 &= ~DFWP; //Close FRAM Write Protection + //FRAM_Date_START=*0x1800; + for (uint8_t i = 0; i < Array_Long; i++) + { + *(uint8_t *)(FRAM_START+i)=Array[i];// + } + SYSCFG0 |= DFWP; //Open FRAM Write Protection +} + +void FRAM_Read (uint16_t FRAM_START,uint8_t *(Array),uint8_t Array_Long) +{ + for (uint8_t i = 0; i < Array_Long; i++) + { + Array[i]=*(uint8_t *)(FRAM_START+i); + } +} diff --git a/RF-AP/Wuhabin/RF-AP-TX.c b/RF-AP/Wuhabin/RF-AP-TX.c new file mode 100644 index 0000000..a0c6477 --- /dev/null +++ b/RF-AP/Wuhabin/RF-AP-TX.c @@ -0,0 +1,395 @@ +// Haybin_Wu +// Shenitech-RD +// 2016.5 +// Built with IAR Embedded Workbench v6.2 +//****************************************************************************** +#include +#include +#include "FR2433-RFSX.h" +#include "RF_SX1276.h" + +uint32_t t=0; +void FRAM_Write (uint16_t FRAM_START,uint8_t *(Array),uint8_t Array_Long); +void FRAM_Read (uint16_t FRAM_START,uint8_t *(Array),uint8_t Array_Long); +void Set_DT(void); +void Refresh_Date(void); +void UART0_Tx(uint8_t data); + +#define FRAM_Date_START 0x1800 //Date 洢ʼַ +#define FRAM_ID_START 0x1806 //ID 洢ʼַ +#define RTC_Data 1920 //RTCʱ RTC_Data/32=s + +uint8_t Rx_Buf[64]; +uint8_t Rx_Length=0; +uint8_t Rx_Flog=0; +uint8_t Rx_Data=0; +uint8_t Date_Time[6]= +{ + 30,//0 + 16,//1 + 10,//2ʱ + 22,//3 + 05,//4 + 16,//5 +}; +uint8_t Device_ID[4]={0xA6,0x52,0x40,0x01,};//豸ID + + //UART + void UART0_Tx(uint8_t data) + { + UCA0TXBUF = data; + while((UCTXIFG&UCA0IFG)==0); + UCA0IFG&=~UCTXIFG; + } + void Refresh_Date(void) + { + FRAM_Read(FRAM_Date_START,Date_Time,6); + Date_Time[0]=RTCCNT/32; + } + +//////////////////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////////////////// + int main(void) +{ + WDTCTL = WDTPW | WDTHOLD; // Stop WDT + // Port Configuration all un-used pins to output low + P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; + P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; + PM5CTL0 &= ~LOCKLPM5;//Ź + + // Configure DCO Clock +//ⲿʱԴ + P2SEL0 |= BIT0 | BIT1; // set XT1 pin as second function + do + { + CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag + SFRIFG1 &= ~OFIFG; + } while (SFRIFG1 & OFIFG); // Test oscillator fault flag + //־ڽ͹ + + __bis_SR_register(SCG0); // disable FLL + CSCTL3 |= SELREF__XT1CLK; // ⲿ 32768hz reference source + CSCTL0 = 0; // clear DCO and MOD registers + CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first + CSCTL1 |= DCORSEL_3; //DCO=8Mhz + CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz + __delay_cycles(3); + __bic_SR_register(SCG0); // enable FLL + while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked + + CSCTL4 = SELREF__XT1CLK + SELMS__DCOCLKDIV;// set XT1CLK(32768Hz) as ACLK source & MCLK/SMCLK=DCO + + + + + //Timer0_A3 setup + //TA0CCTL0 = CCIE; // TACCR0 interrupt enabled + //TA0CCR0 = 32768; + //TA0CTL = TASSEL_1 | MC_1; // ACLK, continuous mode + + // Initialize RTC + RTCMOD = RTC_Data; + RTCCTL = (RTCSS__XT1CLK + RTCPS__1024 + RTCIE);//+ RTCSR// Source = 32kHz crystal, divided by 1024 + if(RTCCNT>RTC_Data){RTCCTL |= RTCSR;WDTCTL=0;} + Refresh_Date();//λˢʱ + //FRCTL0 = FRCTLPW | NWAITS_1;//FRRAM + FRAM_Read(FRAM_ID_START,Device_ID,4);//ˢ豸ID + + + // Configure UART pins + P1SEL0 |= BIT4 | BIT5; // set 2-UART pin as second function + // Configure UART + UCA0CTLW0 |=(UCSSEL__SMCLK+UCSWRST);//UCPEN+UCPAR+ + // Baud Rate calculation + UCA0BR0 = 52; // 8000000/8/9600//λ16 UCOS16λҪλ + UCA0BR1 = 0x00; // Fractional portion = 0.083 + //UCA0MCTLW = 0x11;//΢Baud Rate + UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1;//΢Baud Rate + UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI + UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt + + _EINT(); + + //ģԻ + uint8_t RF_error_flag=0; + for(uint8_t i=0;i<5;i++)//ʼ3 + { + if(SX127x_init(Init_LoRa_0_8K)==NORMAL) break; //ģʼʧܸλ + else RF_error_flag=1; + } + if(RF_error_flag==1) //߳ʼʧܴ + { + //P3OUT ^= 0xC0; + LPM4; + } + LSD_RF_SleepMode();//˯1.2uA + + + __bis_SR_register(LPM3_bits | GIE); // Enter LPM3 + //uint32_t i=0; + __no_operation(); // For debugger + + while(1) + { + //P3OUT ^= 0xC0; + //for(uint8_t i=0;i= 100) + { + Rx_Length = 0; + } + Rx_Buf[Rx_Length]=UCA0RXBUF; + Rx_Length++; + Rx_Flog=1; +} + + +// SPI-B0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=USCI_B0_VECTOR +__interrupt void USCI_B0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + while (!(UCB0IFG&UCTXIFG)); // USCI_A0 TX buffer ready? + UCB0TXBUF = UCB0RXBUF; // Echo received data +} +*/ + +// Timer0 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER0_A0_VECTOR +__interrupt void Timer0_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) Timer0_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + t++; + if(t>5) + { + t=0;//WDTCTL=0; + //LSD_RF_RxVariPacket(Rxbuffer,Rxbuffer_size); //տɱݰΪʣֻýչ̶ݰ + //LSD_RF_RXmode(30); //ÿηһݺ󣬽״̬ȴBģӦ + + } +} +// Timer1 A0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector = TIMER1_A0_VECTOR +__interrupt void Timer1_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(TIMER1_A0_VECTOR))) Timer1_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + ; + //if(t>5)WDTCTL=0;//P3OUT ^= 0xC0; +} + +// RTC interrupt service routine //һһ +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=RTC_VECTOR +__interrupt void RTC_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(RTC_VECTOR))) RTC_ISR (void) +#else +#error Compiler not supported! +#endif +{ + if(RTCIV&0x02) + { + Date_Time[0]=60; + Set_DT();// + FRAM_Write (FRAM_Date_START,Date_Time,6);//д + } +} + +// UAR0 interrupt service routine +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) +#pragma vector=USCI_A0_VECTOR +__interrupt void USCI_A0_ISR(void) +#elif defined(__GNUC__) +void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void) +#else +#error Compiler not supported! +#endif +{ + uint8_t CS=0; + if((UCA0IV&USCI_UART_UCRXIFG)==USCI_UART_UCRXIFG) + { + Rx_Flog=1; + Rx_Buf[Rx_Data] = UCA0RXBUF; + Rx_Data++; + //UCA0IFG&=~UCRXIFG; + } + if(Rx_Data>=10) + { + for(uint8_t i=0;i<(Rx_Buf[3]+1);i++) + CS+=Rx_Buf[i+2]; + if((Rx_Buf[0]==0x4D)&&(Rx_Buf[1]==0x4B)&&(Rx_Buf[Rx_Data-2]==0x55)&&(Rx_Buf[Rx_Data-1]==0x16)) + { + FRAM_Read(FRAM_ID_START,Device_ID,4);//ˢ豸ID + //01 ID//4D 4B 01 08 00 00 00 00 ID ID ID ID CS 16 + if((Rx_Buf[2]==0x01)&&(Rx_Buf[4]==Device_ID[0])&&(Rx_Buf[5]==Device_ID[1])&&(Rx_Buf[6]==Device_ID[2])&&(Rx_Buf[7]==Device_ID[3])) + { + Device_ID[0]=Rx_Buf[8];Device_ID[1]=Rx_Buf[9];Device_ID[2]=Rx_Buf[10];Device_ID[3]=Rx_Buf[11]; + FRAM_Write(FRAM_ID_START,Device_ID,4); + //FRAM_Read(FRAM_ID_START,Device_ID,4);//ˢ豸ID + UART0_Tx(0xE5); + } + //06 豸RTC//4D 4B 06 04 00 00 00 00 CS 16 + if((Rx_Buf[2]==0x06)&&(Rx_Buf[4]==Device_ID[0])&&(Rx_Buf[5]==Device_ID[1])&&(Rx_Buf[6]==Device_ID[2])&&(Rx_Buf[7]==Device_ID[3])) + { + Refresh_Date();//refresh time + //Return 4D 4B 06 A0 ID ID ID ID DT DT DT DT DT DT E5 16 + UART0_Tx(0x4D);UART0_Tx(0x4B);UART0_Tx(0x06);UART0_Tx(0xA0);UART0_Tx(Device_ID[0]);UART0_Tx(Device_ID[1]);UART0_Tx(Device_ID[2]);UART0_Tx(Device_ID[3]); + UART0_Tx(Date_Time[0]);UART0_Tx(Date_Time[1]);UART0_Tx(Date_Time[2]);UART0_Tx(Date_Time[3]);UART0_Tx(Date_Time[4]);UART0_Tx(Date_Time[5]); + UART0_Tx(0xE5);UART0_Tx(0x16); + } + //07 ͬRTC//4D 4B 06 04 00 00 00 00 CS 16 + if((Rx_Buf[2]==0x07)&&(Rx_Buf[4]==Device_ID[0])&&(Rx_Buf[5]==Device_ID[1])&&(Rx_Buf[6]==Device_ID[2])&&(Rx_Buf[7]==Device_ID[3])) + { + ; + } + } + + __bic_SR_register_on_exit(LPM3_bits); // Exit LPM3 + + } +} + + +// +void Set_DT(void) +{ + + if(Date_Time[0]>59)//λ + { + Date_Time[1]++; + Date_Time[0]=0; + } + if(Date_Time[1]>59)//ֽλ + { + Date_Time[2]++; + Date_Time[1]=0; + } + if(Date_Time[2]>23)//Сʱλ + { + Date_Time[3]++; + Date_Time[2]=0; + } +//31 +if((Date_Time[4]==1)||(Date_Time[4]==3)||(Date_Time[4]==5)||(Date_Time[4]==7)||(Date_Time[4]==8)||(Date_Time[4]==10)||(Date_Time[4]==12)) +{ + if(Date_Time[3]>31) + { + Date_Time[3]=1; + Date_Time[4]++; + } + if(Date_Time[4]>12) + { + Date_Time[4]=1; + Date_Time[5]++; + } + if(Date_Time[5]>99)Date_Time[5]=0; +} +//30 +if((Date_Time[4]==4)||(Date_Time[4]==6)||(Date_Time[4]==9)||(Date_Time[4]==11)) +{ + if(Date_Time[3]>30) + { + Date_Time[3]=1; + Date_Time[4]++; + } +} +//2 +if(Date_Time[4]==2) +{ + if((Date_Time[5]%4==0&&Date_Time[5]%100!=0) ||(Date_Time[5]%400==0))// + { + if(Date_Time[3]>29) + { + Date_Time[3]=1; + Date_Time[4]++; + } + } + else + { + if(Date_Time[3]>28) + { + Date_Time[3]=1; + Date_Time[4]++; + } + } + } +} + +void FRAM_Write (uint16_t FRAM_START,uint8_t *(Array),uint8_t Array_Long) +{ + SYSCFG0 &= ~DFWP; //Close FRAM Write Protection + //FRAM_Date_START=*0x1800; + for (uint8_t i = 0; i < Array_Long; i++) + { + *(uint8_t *)(FRAM_START+i)=Array[i];// + } + SYSCFG0 |= DFWP; //Open FRAM Write Protection +} + +void FRAM_Read (uint16_t FRAM_START,uint8_t *(Array),uint8_t Array_Long) +{ + for (uint8_t i = 0; i < Array_Long; i++) + { + Array[i]=*(uint8_t *)(FRAM_START+i); + } +} diff --git a/RF-AP/资料及文档/SX127X参考例程/LSD_RF_SX1276.c b/RF-AP/资料及文档/SX127X参考例程/LSD_RF_SX1276.c new file mode 100644 index 0000000..2ffcea0 --- /dev/null +++ b/RF-AP/资料及文档/SX127X参考例程/LSD_RF_SX1276.c @@ -0,0 +1,264 @@ +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: ƼŹɷ޹˾ +// ļ: +// 汾 v2.0 +// : IAR v5.30 +// : ں +// : 2013.12 +// : API +// ļ: +// ޸־ +// ˵ +//////////////////////////////////////////////////////////////////////////////// +#include +#include +#include "sx1276-LoRa.h" +#include "sx1276-f4152-Hal.h" +#include "LSD_RF_SX1276.h" +//====================================================================================== +float G_BandWidthKHz = 500.0;//ؼSymbolʹ +float G_TsXms = 1.024;//1.024ms +S_LoRaConfig G_LoRaConfig = { + 470000000, + BW500KHZ, + SF08, + CR_4_5, + 15, + true, + true, + true, + 64, +}; + +bool LoRaConfig_Check() +{ + if((G_LoRaConfig.LoRa_Freq<137000000)||(G_LoRaConfig.LoRa_Freq>525000000)) + return false; + G_LoRaConfig.BandWidth = (t_BandWidth)(G_LoRaConfig.BandWidth&0xF0); + if(G_LoRaConfig.BandWidth>BW500KHZ) + return false; + //BandWidth + switch(G_LoRaConfig.BandWidth){ + case BW500KHZ:G_BandWidthKHz = 500.0;break; + case BW250KHZ:G_BandWidthKHz = 250.0;break; + case BW125KHZ:G_BandWidthKHz = 125.0;break; + case BW62_50KHZ:G_BandWidthKHz = 62.5;break; + case BW41_66KHZ:G_BandWidthKHz = 41.66;break; + case BW31_25KHZ:G_BandWidthKHz = 31.25;break; + case BW20_83KHZ:G_BandWidthKHz = 20.83;break; + case BW15_62KHZ:G_BandWidthKHz = 15.62;break; + case BW10_41KHZ:G_BandWidthKHz = 10.41;break; + case BW7_81KHZ:G_BandWidthKHz = 7.81;break; + } + G_LoRaConfig.SpreadingFactor = (t_SpreadingFactor)(G_LoRaConfig.SpreadingFactor&0xF0); + if((G_LoRaConfig.SpreadingFactor>SF12)||(G_LoRaConfig.SpreadingFactor>4)-1))/G_BandWidthKHz; + + G_LoRaConfig.CodingRate = (t_CodingRate)(G_LoRaConfig.CodingRate&0x0E); + if((G_LoRaConfig.CodingRate>CR_4_8)||(G_LoRaConfig.CodingRate15) + return false; + if(G_LoRaConfig.PayloadLength>127) + return false; + return true; +} +//===================================Ӻ=================================================== +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : tSX127xInitPara initPara Init_LoRa_0_8K, Init_LoRa_4_8K , Init_LoRa_10k, +// ز : tSX127xError ö +// ˵ : ʼʱŵʼĬΪ0ŵ +//////////////////////////////////////////////////////////////////////////////// + +tSX127xError SX127x_init() +{ + if(false==LoRaConfig_Check()) // + { + return PARAMETER_INVALID; // + } + SX1276InitIo(); // PAIOڳʼ + SX1276Reset(); //λRF + SX1276SPISetup(); //SPIʼ + + //лLoRamodestandby״̬ + SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + + /*------------------------------------------------ + SPI ֤ */ + uint8_t test = 0; + SX1276Write( REG_LR_HOPPERIOD,0x91 );//ѡһòļĴ֤ + SX1276Read( REG_LR_HOPPERIOD,&test); + if(test!=0x91) + return SPI_READCHECK_WRONG; + SX1276Write( REG_LR_DIOMAPPING2, RFLR_DIOMAPPING2_DIO4_01); + //Frequency Configuration + LSD_RF_FreqSet(); //Ƶ + + //PA Configuration + LSD_RF_PoutSet(); + SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_0100_US); + // PA Rampʱ䣬ûLDOܿʵPA Rampʱ + // Rampʱ̳LDOʱֽTXϵͳΪRFźŲֵ + SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);//ر Over Current Protection + + //PayloadLength ʼ + SX1276Write( REG_LR_PAYLOADLENGTH,G_LoRaConfig.PayloadLength); + //ע⣬ͷģʽImplicit Headerʱǰ涨շ˫PL + + //BWCRHeaderޣʼ + SX1276Write( REG_LR_MODEMCONFIG1,\ + (((uint8_t)G_LoRaConfig.BandWidth)|((uint8_t)G_LoRaConfig.CodingRate))|(\ + (true==G_LoRaConfig.ExplicitHeaderOn)?0x00:0x01)); + + //SFCRCʼ + SX1276Write( REG_LR_MODEMCONFIG2,\ + ((uint8_t)G_LoRaConfig.SpreadingFactor)|(\ + (true==G_LoRaConfig.CRCON)?0x04:0x00)); + if(SF06==G_LoRaConfig.SpreadingFactor){ //SF = 6Ҫú + uint8_t temp = 0; + SX1276Read( 0x31,&temp); + SX1276Write( 0x31,(temp& 0xF8)|0x05); + SX1276Write( 0x37,0x0C); + } + + //ŻǷAutoAGCĬϿ + SX1276Write( REG_LR_MODEMCONFIG3,((G_TsXms>16.0)?\ + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON:RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF\ + )|RFLR_MODEMCONFIG3_AGCAUTO_ON); + return NORMAL; +} +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ +// ز : +// ˵ : Ϊǣ preambleĻĬֵ +//////////////////////////////////////////////////////////////////////////////// +void SX1276_TxPacket(uint8_t*data) +{ + + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,10); + SX1276Write( REG_LR_PAYLOADLENGTH,G_LoRaConfig.PayloadLength); + SX1276WriteRxTx(true); + SX1276Write( REG_LR_FIFOADDRPTR,0x80); + SX1276WriteBuffer(REG_LR_FIFO,data,G_LoRaConfig.PayloadLength); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : +// ز : +// ˵ : պpreambleûĬֵΪ +//////////////////////////////////////////////////////////////////////////////// +void Rx_mode() +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_PREAMBLEMSB,0); + SX1276Write( REG_LR_PREAMBLELSB,10); + SX1276Write( REG_LR_PAYLOADLENGTH,G_LoRaConfig.PayloadLength); + SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE)); + SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 ); + SX1276WriteRxTx(false); + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + SX1276Write(REG_LR_IRQFLAGS,0xff); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*cbufָ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxPacket(uint8_t*cbuf) +{ + if(true==G_LoRaConfig.ExplicitHeaderOn){ + //ͷôӼĴжG_LoRaConfigóȶȡFIFO + SX1276Read(REG_LR_NBRXBYTES,&G_LoRaConfig.PayloadLength); + SX1276Write( REG_LR_FIFOADDRPTR,0x00); + } + SX1276ReadFifo(cbuf,G_LoRaConfig.PayloadLength); + SX1276Write(REG_LR_IRQFLAGS,0xff); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFSLEEP״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SleepMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFstandby״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_StandbyMode(void) +{ + SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY ); +} +//////////////////////////////////////////////////////////////////////////////// +// : RFƵ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +tSX127xError LSD_RF_FreqSet() +{ + + if((G_LoRaConfig.LoRa_Freq>525000000)||(G_LoRaConfig.LoRa_Freq<137000000)) + return PARAMETER_INVALID; + uint32_t freq_reg = (uint32_t)(G_LoRaConfig.LoRa_Freq/FREQ_STEP); + uint8_t test_FRFMSB = 0,test_FRFMID=0,test_FRFLSB=0; + LSD_RF_StandbyMode(); + // FREQ = 474.6MHz + SX1276Write( REG_LR_FRFMSB, (uint8_t)(freq_reg>>16));//Carrier Freq 470M + SX1276Write( REG_LR_FRFMID, (uint8_t)(freq_reg>>8) ); + SX1276Write( REG_LR_FRFLSB, (uint8_t)(freq_reg) ); + + SX1276Read(REG_LR_FRFMSB,&test_FRFMSB); + SX1276Read(REG_LR_FRFMID,&test_FRFMID); + SX1276Read(REG_LR_FRFLSB,&test_FRFLSB); + + if(test_FRFMSB != (uint8_t)(freq_reg>>16)) + return SPI_READCHECK_WRONG; + if(test_FRFMID != (uint8_t)(freq_reg>>8)) + return SPI_READCHECK_WRONG; + if(test_FRFLSB != (uint8_t)(freq_reg)) + return SPI_READCHECK_WRONG; + return NORMAL; +} +//////////////////////////////////////////////////////////////////////////////// +// : RFù +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +tSX127xError LSD_RF_PoutSet() +{ + if(G_LoRaConfig.PowerCfig>15) + return PARAMETER_INVALID; + LSD_RF_StandbyMode(); + SX1276Write( REG_LR_PACONFIG, 0xf0|G_LoRaConfig.PowerCfig); + uint8_t test = 0; + SX1276Read(REG_LR_PACONFIG,&test); + if((0xf0|G_LoRaConfig.PowerCfig)!=test) + return SPI_READCHECK_WRONG; + if(true==G_LoRaConfig.MaxPowerOn) + SX1276Write( REG_LR_PADAC, 0x80|RFLR_PADAC_20DBM_ON ); + else + SX1276Write( REG_LR_PADAC, 0x80|RFLR_PADAC_20DBM_OFF ); + return NORMAL; +} diff --git a/RF-AP/资料及文档/SX127X参考例程/LSD_RF_SX1276.h b/RF-AP/资料及文档/SX127X参考例程/LSD_RF_SX1276.h new file mode 100644 index 0000000..73d2643 --- /dev/null +++ b/RF-AP/资料及文档/SX127X参考例程/LSD_RF_SX1276.h @@ -0,0 +1,133 @@ +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: ƼŹɷ޹˾ +// ļ: +// 汾 v1.0 +// : IAR v5.30 +// : ١Dzں +// : 2013.12 +// : API +// ļ: +// ޸־ +//////////////////////////////////////////////////////////////////////////////// + +#ifndef LSD_RF_SX1276_H +#define LSD_RF_SX1276_H +//====================================================================================== + +typedef enum +{ + NORMAL, // + PARAMETER_INVALID, // + SPI_READCHECK_WRONG, //SPI +}tSX127xError; //ö + +typedef enum +{ + // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz, + // 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved] + BW500KHZ = 0x90, + BW250KHZ = 0x80, + BW125KHZ = 0x70, + BW62_50KHZ = 0x60, + BW41_66KHZ = 0x50, + BW31_25KHZ = 0x40, + BW20_83KHZ = 0x30, + BW15_62KHZ = 0x20, + BW10_41KHZ = 0x10, + BW7_81KHZ = 0x00, +}t_BandWidth; //ö +typedef enum{ + // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips] + SF12 = 0xC0, + SF11 = 0xB0, + SF10 = 0xA0, + SF09 = 0x90, + SF08 = 0x80, + SF07 = 0x70, + SF06 = 0x60, +}t_SpreadingFactor; +typedef enum{ + // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + CR_4_8 = 0x08, + CR_4_7 = 0x06, + CR_4_6 = 0x04, + CR_4_5 = 0x02, +}t_CodingRate; +typedef struct S_LoRaConfig +{ + uint32_t LoRa_Freq; + t_BandWidth BandWidth; + t_SpreadingFactor SpreadingFactor; + t_CodingRate CodingRate; + int8_t PowerCfig; //0~15, = 2+PowerReg,οֲ + //MaxPowerPowerReg = 15ʱ = 191dBm + bool MaxPowerOn; // [false: OFF, true: ON] + bool CRCON; // [false: OFF, true: ON] + bool ExplicitHeaderOn; // [false: OFF, true: ON] + uint8_t PayloadLength; //1~127 +}S_LoRaConfig; + +extern S_LoRaConfig G_LoRaConfig; +extern float G_BandWidthKHz;//Symbolʹ +extern float G_TsXms;//Symbolڣλms + +//====================================================================================== +//////////////////////////////////////////////////////////////////////////////// +// : RFʼ +// : +// ز : tSX127xError ö +// ˵ : ʼʱȫֱG_LoRaConfig +//////////////////////////////////////////////////////////////////////////////// +tSX127xError SX127x_init(); +//////////////////////////////////////////////////////////////////////////////// +// : RFݰ +// : uint8_t*dataָ룬uint8_t sizeݳ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void SX1276_TxPacket(uint8_t*data); +void SX1276_Process(void); +//////////////////////////////////////////////////////////////////////////////// +// : RF״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void Rx_mode(void); +//////////////////////////////////////////////////////////////////////////////// +// : RFտɱݰ +// : uint8_t*cbufָ +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_RxPacket(uint8_t*cbuf); +//////////////////////////////////////////////////////////////////////////////// +// : RFSLEEP״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_SleepMode(void); +//////////////////////////////////////////////////////////////////////////////// +// : RFstandby״̬ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +void LSD_RF_StandbyMode(void); +//////////////////////////////////////////////////////////////////////////////// +// : RFƵ +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +tSX127xError LSD_RF_FreqSet(); +//////////////////////////////////////////////////////////////////////////////// +// : RFù +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +tSX127xError LSD_RF_PoutSet(); +//***************************************************************************************** +#endif \ No newline at end of file diff --git a/RF-AP/资料及文档/SX127X参考例程/main_TX.c b/RF-AP/资料及文档/SX127X参考例程/main_TX.c new file mode 100644 index 0000000..0b7bd5a --- /dev/null +++ b/RF-AP/资料及文档/SX127X参考例程/main_TX.c @@ -0,0 +1,262 @@ +//////////////////////////////////////////////////////////////////////////////// +// Ȩ: ƼŹɷ޹˾ +// ļ: main_tx/rx +// 汾 v1.0 +// : IAR v5.30 +// : ں +// : 2013.12 +// : AͰǸBƵ˸Bģӵݺ˸BݻشAģ飬 +// Aӵݺ˸ ѭβ +// ļ: +// ޸־ +//////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include "driver.h" +#include "sx1276-f4152-Hal.h" +#include "LSD_RF_SX1276.h" +#include "LSD_RF_APPrf.h" +#include "clock.h" +//====================================================================================== +long SysTick = 0; +uint8_t TXbuffer[30]={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29}; +uint8_t WakeAddr[8]={5,6,7,8,9,10,11,7}; +uint8_t Rxbuffer[64]; +//====================================================================================== + +//=============================================================================================== +//////////////////////////////////////////////////////////////////////////////// +// : +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +typedef enum{ + Nope, + B300bps,//BW = 500KHz SF = 7 CR = 4_6 + B1080bps,//BW = 125KHz SF = 9 CR = 4_6 + B4000bps,//BW = 125KHz SF = 7 CR = 4_5 +}t_Baudrate; +t_Baudrate Baudrate = Nope; + +unsigned char *point; +unsigned char Reg_PKTSNR = 0; +unsigned char Reg_PKTRssi = 0; +unsigned char Reg_Rssi = 0; + +unsigned char LCD_p[9] = {0,0,0,0,0,8,0,1,0xff}; +int T_Cnt = 0; +int R_Cnt = 0; +bool RESET_Flag = false; +void main( void ) +{ + WDTCTL = WDTPW + WDTHOLD; // رտŹ + platform_init(); //Եװʼ + LEDONBAND(LEDALL); //ʼ̵LED + KEYBOARD_DIR &=~ (KEY_S1+KEY_S2); + KEYBOARD_IFG &=~ (KEY_S1+KEY_S2); + KEYBOARD_IES |= (KEY_S1+KEY_S2); + KEYBOARD_IE |= (KEY_S1+KEY_S2); + + point = (unsigned char *)(&(G_LoRaConfig.BandWidth)); + flash_read(FLASH_ADDRESS_D,point,3*2); + if(G_LoRaConfig.BandWidth>BW500KHZ){ + G_LoRaConfig.BandWidth=BW125KHZ; + G_LoRaConfig.SpreadingFactor = SF09; + G_LoRaConfig.CodingRate = CR_4_6; + flash_seg_clear(FLASH_ADDRESS_D);//д֮ǰ + flash_write(FLASH_ADDRESS_D,point,3*2); + } + if(G_LoRaConfig.SpreadingFactor==SF11){ + Baudrate = B300bps; + LCD_p[8] = 1; + } + else{ + if(G_LoRaConfig.SpreadingFactor==SF07){ + Baudrate = B4000bps; + LCD_p[8] = 3; + } + else{ + Baudrate = B1080bps; + LCD_p[8] = 2; + } + } + LCD_p[7] = 0xff;LCD_p[6] = 0;LCD_p[5] = 0;LCD_p[4] = 0; + lcd_init(); + LCD_Disp_ALL_Num(LCD_p); + //ø + G_LoRaConfig.LoRa_Freq = 474600000; //Ƶ470MHz + //G_LoRaConfig.BandWidth = BW125KHZ; //BW = 125KHz + //G_LoRaConfig.SpreadingFactor = SF09; //SF = 9 + //G_LoRaConfig.CodingRate = CR_4_6; //CR = 4/6 + G_LoRaConfig.PowerCfig = 15; //19dBm + G_LoRaConfig.MaxPowerOn = true; + G_LoRaConfig.CRCON = true; //CRC + G_LoRaConfig.ExplicitHeaderOn = true; //Header + G_LoRaConfig.PayloadLength = 20; //ݰ + + if(SX127x_init()!=NORMAL) WDTCTL=0; //ģʼʧܸλ + KEYBOARD_IE |= (KEY_S1+KEY_S2); + _EINT(); //ж + LEDOFFBIT(LEDALL); //ʼϹرLED + ON_Timerout(); //ʱ1sһ + while(1) + { + LPM3; + if(RESET_Flag==true){ + flash_seg_clear(FLASH_ADDRESS_D);//д֮ǰ + flash_write(FLASH_ADDRESS_D,point,3*2); + WDTCTL = 0;//RESET + } + + LSD_RF_RXmode(); //ÿηһݺ󣬽״̬ȴBģӦ + /****RSSI*****/ + + //жѾ + LCD_p[6] = Reg_PKTRssi/100%10; + LCD_p[5] = Reg_PKTRssi/10%10; + LCD_p[4] = Reg_PKTRssi%10; + + LCD_p[0] = T_Cnt%10; + LCD_p[1] = T_Cnt/10%10; + LCD_p[2] = R_Cnt%10; + LCD_p[3] = R_Cnt/10%10; + /****Cnt *****/ + //LCD_p[0] = T_Cnt%10; + //LCD_p[1] = T_Cnt/10%10; + //LCD_p[2] = R_Cnt%10; + //LCD_p[3] = R_Cnt/10%10; + LCD_ClrLcd_ALL(); + LCD_Disp_ALL_Num(LCD_p); + if(T_Cnt>=100) + T_Cnt = 0; + if(R_Cnt>=100) + R_Cnt = 0; + } +} +//////////////////////////////////////////////////////////////////////////////// +// : ߽ж +// : +// ز : +// ˵ : +//////////////////////////////////////////////////////////////////////////////// +#pragma vector = PORT1_VECTOR +__interrupt void port1_isr(void) +{ + if(KEYBOARD_IFG&(KEY_ALL)){ + char Keys_Flag = KEYBOARD_IFG&(KEY_ALL); + switch(Keys_Flag&(KEY_S1|KEY_S2)){ + case KEY_S1: + switch(Baudrate){ + case B1080bps: + G_LoRaConfig.BandWidth = BW125KHZ; //BW = 125KHz + G_LoRaConfig.SpreadingFactor = SF07; //SF = 9 + G_LoRaConfig.CodingRate = CR_4_6; //CR = 4/6 + Baudrate = B4000bps; + break; + case B4000bps: + G_LoRaConfig.BandWidth = BW125KHZ; //BW = 125KHz + G_LoRaConfig.SpreadingFactor = SF11; //SF = 9 + G_LoRaConfig.CodingRate = CR_4_8; //CR = 4/6 + Baudrate = B300bps; + break; + case B300bps: + default: + G_LoRaConfig.BandWidth = BW125KHZ; //BW = 125KHz + G_LoRaConfig.SpreadingFactor = SF09; //SF = 9 + G_LoRaConfig.CodingRate = CR_4_6; //CR = 4/6 + Baudrate = B1080bps; + break; + } + RESET_Flag = true; + LPM3_EXIT; + break; + case KEY_S2: + T_Cnt = 0; + R_Cnt = 0; + break; + default: + break; + } + KEYBOARD_IFG &= ~KEY_ALL; + return; + } + if(DIO0_IFG) //жǷDIO0ж + { + DIO0_IFG = 0; //DIO0жϱ־λ + + LSD_RF_RxPacket(Rxbuffer); //ݰ +#include "sx1276-LoRa.h" + signed int temp = 0,test; + SX1276Read( REG_LR_PKTSNRVALUE,&Reg_PKTSNR); + test = (signed char)Reg_PKTSNR; + if((Reg_PKTSNR&0x80)!=0){// + //LCD_p[3] = 10;//Reg_PKTSNR + Reg_PKTSNR = ~(Reg_PKTSNR)+1; + temp = -Reg_PKTSNR; + } + else{ + //LCD_p[3] = 0xff;//Reg_PKTSNR + temp = Reg_PKTSNR; + } + test++; + SX1276Read( REG_LR_PKTRSSIVALUE,&Reg_PKTRssi); + if(temp>0){ + temp = -164+Reg_PKTRssi*16/15; + //if(temp>-50) + //temp = -137+Reg_PKTRssi; + } + else{ + temp = -164+Reg_PKTRssi+(signed char)(temp*0.25+0.5); + } + if(temp<0){ + LCD_p[7] = 10; + Reg_PKTRssi = -temp; + } + else{ + LCD_p[7] = 0xff; + Reg_PKTRssi = temp; + } + //SX1276Read( REG_LR_RSSIVALUE,&Reg_Rssi); + //Reg_Rssi + if(memcmp(Rxbuffer,TXbuffer,20)==0) + { + LEDONBIT(LED1); //״ָ̬ʾ + DelayMs(60); + LEDOFFBIT(LED1); //״ָ̬ʾ + R_Cnt++; + } + LPM3_EXIT; + } + P1IFG=0; +} +//////////////////////////////////////////////////////////////////////////////// +// : ʱʱ +// : +// ز : +// ˵ : ѣʧܺʱʱ䵽½WOR +//////////////////////////////////////////////////////////////////////////////// +#pragma vector = TIMER1_A0_VECTOR +__interrupt void Timer1_A0_ISR() +{ + static uint8 t=0; + t++; + if(Baudrate >= B1080bps) + t = 5; + if(Baudrate == B300bps) + t++; + if(t >= 5) + { + LEDONBIT(LED3);//״ָ̬ʾ + G_LoRaConfig.PayloadLength = 20; + SX1276Reset(); + if(SX127x_init()!=NORMAL) WDTCTL=0; + LSD_RF_SendPacket(TXbuffer);//30ֽݲ + T_Cnt++; + LEDOFFBIT(LED3);//״ָ̬ʾ + LPM3_EXIT; + t = 0; + } +} diff --git a/RF-AP/资料及文档/SX127X参考例程/sx1276-LoRa.h b/RF-AP/资料及文档/SX127X参考例程/sx1276-LoRa.h new file mode 100644 index 0000000..011a864 --- /dev/null +++ b/RF-AP/资料及文档/SX127X参考例程/sx1276-LoRa.h @@ -0,0 +1,880 @@ + +#ifndef __SX1276_LORA_H__ +#define __SX1276_LORA_H__ + +/*! + * SX1276 LoRa General parameters definition + */ +typedef struct sLoRaSettings +{ + uint32_t RFFrequency; + int8_t Power; + uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz, + // 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved] + uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips] + uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + bool CrcOn; // [0: OFF, 1: ON] + bool ImplicitHeaderOn; // [0: OFF, 1: ON] + bool RxSingleOn; // [0: Continuous, 1 Single] + bool FreqHopOn; // [0: OFF, 1: ON] + uint8_t HopPeriod; // Hops every frequency hopping period symbols + uint32_t TxPacketTimeout; + uint32_t RxPacketTimeout; + uint8_t PayloadLength; +}tLoRaSettings; + +/*! + * RF packet definition + */ +#define RF_BUFFER_SIZE_MAX 128 +#define RF_BUFFER_SIZE 80 + +/*! + * RF state machine + */ +//LoRa +typedef enum +{ + RFLR_STATE_IDLE, + RFLR_STATE_RX_INIT, + RFLR_STATE_RX_RUNNING, + RFLR_STATE_RX_DONE, + RFLR_STATE_RX_TIMEOUT, + RFLR_STATE_TX_INIT, + RFLR_STATE_TX_RUNNING, + RFLR_STATE_TX_DONE, + RFLR_STATE_TX_TIMEOUT, + RFLR_STATE_CAD_INIT, + RFLR_STATE_CAD_RUNNING, +}tRFLRStates; + +/*! + * SX1276 definitions + */ +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +/*! + * SX1276 Internal registers Address + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +//#define REG_LR_BANDSETTING 0x04 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_NBRXBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 + + +/*! + * SX1276 LoRa bit control definition + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegBandSetting + */ +#define RFLR_BANDSETTING_MASK 0x3F +#define RFLR_BANDSETTING_AUTO 0x00 // Default +#define RFLR_BANDSETTING_DIV_BY_1 0x40 +#define RFLR_BANDSETTING_DIV_BY_2 0x80 +#define RFLR_BANDSETTING_DIV_BY_6 0xC0 + +/*! + * RegFrf (MHz) + */ + +#define RFLR_FRFMSB_434_MHZ 0x6C // Default +#define RFLR_FRFMID_434_MHZ 0x80 // Default +#define RFLR_FRFLSB_434_MHZ 0x00 // Default +#define RFLR_FRFMSB_470_MHZ 0x75 +#define RFLR_FRFMID_470_MHZ 0x80 +#define RFLR_FRFLSB_470_MHZ 0x00 +#define RFLR_FRFMSB_475_MHZ 0x76 +#define RFLR_FRFMID_475_MHZ 0xC0 +#define RFLR_FRFLSB_475_MHZ 0x00 + +#define RFLR_FRFMSB_863_MHZ 0xD7 +#define RFLR_FRFMID_863_MHZ 0xC0 +#define RFLR_FRFLSB_863_MHZ 0x00 +#define RFLR_FRFMSB_864_MHZ 0xD8 +#define RFLR_FRFMID_864_MHZ 0x00 +#define RFLR_FRFLSB_864_MHZ 0x00 +#define RFLR_FRFMSB_865_MHZ 0xD8 +#define RFLR_FRFMID_865_MHZ 0x40 +#define RFLR_FRFLSB_865_MHZ 0x00 +#define RFLR_FRFMSB_866_MHZ 0xD8 +#define RFLR_FRFMID_866_MHZ 0x80 +#define RFLR_FRFLSB_866_MHZ 0x00 +#define RFLR_FRFMSB_867_MHZ 0xD8 +#define RFLR_FRFMID_867_MHZ 0xC0 +#define RFLR_FRFLSB_867_MHZ 0x00 +#define RFLR_FRFMSB_868_MHZ 0xD9 +#define RFLR_FRFMID_868_MHZ 0x00 +#define RFLR_FRFLSB_868_MHZ 0x00 +#define RFLR_FRFMSB_869_MHZ 0xD9 +#define RFLR_FRFMID_869_MHZ 0x40 +#define RFLR_FRFLSB_869_MHZ 0x00 +#define RFLR_FRFMSB_870_MHZ 0xD9 +#define RFLR_FRFMID_870_MHZ 0x80 +#define RFLR_FRFLSB_870_MHZ 0x00 + +#define RFLR_FRFMSB_902_MHZ 0xE1 +#define RFLR_FRFMID_902_MHZ 0x80 +#define RFLR_FRFLSB_902_MHZ 0x00 +#define RFLR_FRFMSB_903_MHZ 0xE1 +#define RFLR_FRFMID_903_MHZ 0xC0 +#define RFLR_FRFLSB_903_MHZ 0x00 +#define RFLR_FRFMSB_904_MHZ 0xE2 +#define RFLR_FRFMID_904_MHZ 0x00 +#define RFLR_FRFLSB_904_MHZ 0x00 +#define RFLR_FRFMSB_905_MHZ 0xE2 +#define RFLR_FRFMID_905_MHZ 0x40 +#define RFLR_FRFLSB_905_MHZ 0x00 +#define RFLR_FRFMSB_906_MHZ 0xE2 +#define RFLR_FRFMID_906_MHZ 0x80 +#define RFLR_FRFLSB_906_MHZ 0x00 +#define RFLR_FRFMSB_907_MHZ 0xE2 +#define RFLR_FRFMID_907_MHZ 0xC0 +#define RFLR_FRFLSB_907_MHZ 0x00 +#define RFLR_FRFMSB_908_MHZ 0xE3 +#define RFLR_FRFMID_908_MHZ 0x00 +#define RFLR_FRFLSB_908_MHZ 0x00 +#define RFLR_FRFMSB_909_MHZ 0xE3 +#define RFLR_FRFMID_909_MHZ 0x40 +#define RFLR_FRFLSB_909_MHZ 0x00 +#define RFLR_FRFMSB_910_MHZ 0xE3 +#define RFLR_FRFMID_910_MHZ 0x80 +#define RFLR_FRFLSB_910_MHZ 0x00 +#define RFLR_FRFMSB_911_MHZ 0xE3 +#define RFLR_FRFMID_911_MHZ 0xC0 +#define RFLR_FRFLSB_911_MHZ 0x00 +#define RFLR_FRFMSB_912_MHZ 0xE4 +#define RFLR_FRFMID_912_MHZ 0x00 +#define RFLR_FRFLSB_912_MHZ 0x00 +#define RFLR_FRFMSB_913_MHZ 0xE4 +#define RFLR_FRFMID_913_MHZ 0x40 +#define RFLR_FRFLSB_913_MHZ 0x00 +#define RFLR_FRFMSB_914_MHZ 0xE4 +#define RFLR_FRFMID_914_MHZ 0x80 +#define RFLR_FRFLSB_914_MHZ 0x00 +#define RFLR_FRFMSB_915_MHZ 0xE4 // Default +#define RFLR_FRFMID_915_MHZ 0xC0 // Default +#define RFLR_FRFLSB_915_MHZ 0x00 // Default +#define RFLR_FRFMSB_916_MHZ 0xE5 +#define RFLR_FRFMID_916_MHZ 0x00 +#define RFLR_FRFLSB_916_MHZ 0x00 +#define RFLR_FRFMSB_917_MHZ 0xE5 +#define RFLR_FRFMID_917_MHZ 0x40 +#define RFLR_FRFLSB_917_MHZ 0x00 +#define RFLR_FRFMSB_918_MHZ 0xE5 +#define RFLR_FRFMID_918_MHZ 0x80 +#define RFLR_FRFLSB_918_MHZ 0x00 +#define RFLR_FRFMSB_919_MHZ 0xE5 +#define RFLR_FRFMID_919_MHZ 0xC0 +#define RFLR_FRFLSB_919_MHZ 0x00 +#define RFLR_FRFMSB_920_MHZ 0xE6 +#define RFLR_FRFMID_920_MHZ 0x00 +#define RFLR_FRFLSB_920_MHZ 0x00 +#define RFLR_FRFMSB_921_MHZ 0xE6 +#define RFLR_FRFMID_921_MHZ 0x40 +#define RFLR_FRFLSB_921_MHZ 0x00 +#define RFLR_FRFMSB_922_MHZ 0xE6 +#define RFLR_FRFMID_922_MHZ 0x80 +#define RFLR_FRFLSB_922_MHZ 0x00 +#define RFLR_FRFMSB_923_MHZ 0xE6 +#define RFLR_FRFMID_923_MHZ 0xC0 +#define RFLR_FRFLSB_923_MHZ 0x00 +#define RFLR_FRFMSB_924_MHZ 0xE7 +#define RFLR_FRFMID_924_MHZ 0x00 +#define RFLR_FRFLSB_924_MHZ 0x00 +#define RFLR_FRFMSB_925_MHZ 0xE7 +#define RFLR_FRFMID_925_MHZ 0x40 +#define RFLR_FRFLSB_925_MHZ 0x00 +#define RFLR_FRFMSB_926_MHZ 0xE7 +#define RFLR_FRFMID_926_MHZ 0x80 +#define RFLR_FRFLSB_926_MHZ 0x00 +#define RFLR_FRFMSB_927_MHZ 0xE7 +#define RFLR_FRFMID_927_MHZ 0xC0 +#define RFLR_FRFLSB_927_MHZ 0x00 +#define RFLR_FRFMSB_928_MHZ 0xE8 +#define RFLR_FRFMID_928_MHZ 0x00 +#define RFLR_FRFLSB_928_MHZ 0x00 + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 + +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RFLR_LNA_BOOST_LF_GAIN 0x08 +#define RFLR_LNA_BOOST_LF_IP3 0x10 +#define RFLR_LNA_BOOST_LF_BOOST 0x18 + +#define RFLR_LNA_RXBANDFORCE_MASK 0xFB +#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + + + +/*! + * RegFifoRxNbBytes (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueMsb (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueLsb (Read Only) // + */ + + +/*! + * RegRxPacketCntValueMsb (Read Only) // + */ + + + /*! + * RegRxPacketCntValueLsb (Read Only) // + */ + + + /*! + * RegModemStat (Read Only) // + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) // + */ + + + /*! + * RegPktRssiValue (Read Only) // + */ + + +/*! + * RegRssiValue (Read Only) // + */ + + + /*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F + +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 + +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 + +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + + /*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 + +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 + +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + + +/*! + * RegHopChannel (Read Only) + */ +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default + +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40 +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default + +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegModemConfig3 + */ +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +/*! + * RegFormerTemp + */ + +typedef struct sSX1276LR +{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + + uint8_t RegTestReserved02[0x06 - 0x02]; // 0x02-0x05 + // uint8_t RegRes02; // 0x02 + // uint8_t RegRes03; // 0x03 + // uint8_t RegBandSetting; // 0x04 + // uint8_t RegRes05; // 0x05 + + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + + // LoRa registers + uint8_t RegFifoAddrPtr; // 0x0D + uint8_t RegFifoTxBaseAddr; // 0x0E + uint8_t RegFifoRxBaseAddr; // 0x0F + uint8_t RegFifoRxCurrentAddr; // 0x10 + uint8_t RegIrqFlagsMask; // 0x11 + uint8_t RegIrqFlags; // 0x12 + uint8_t RegNbRxBytes; // 0x13 + uint8_t RegRxHeaderCntValueMsb; // 0x14 + uint8_t RegRxHeaderCntValueLsb; // 0x15 + uint8_t RegRxPacketCntValueMsb; // 0x16 + uint8_t RegRxPacketCntValueLsb; // 0x17 + uint8_t RegModemStat; // 0x18 + uint8_t RegPktSnrValue; // 0x19 + uint8_t RegPktRssiValue; // 0x1A + uint8_t RegRssiValue; // 0x1B + uint8_t RegHopChannel; // 0x1C + uint8_t RegModemConfig1; // 0x1D + uint8_t RegModemConfig2; // 0x1E + uint8_t RegSymbTimeoutLsb; // 0x1F + uint8_t RegPreambleMsb; // 0x20 + uint8_t RegPreambleLsb; // 0x21 + uint8_t RegPayloadLength; // 0x22 + uint8_t RegMaxPayloadLength; // 0x23 + uint8_t RegHopPeriod; // 0x24 + uint8_t RegFifoRxByteAddr; // 0x25 + uint8_t RegModemConfig3; // 0x26 + uint8_t RegTestReserved27[0x31 - 0x27]; // 0x27-0x30 + //void SX1276LoRaSetNbTrigPeaks( uint8_t value )õ + uint8_t RegTestReserved31; // 0x31 + uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x3F + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + + uint8_t RegTestReserved43[0x4B - 0x43]; // 0x43-0x4A + uint8_t RegTcxo; // 0x4B + uint8_t RegTestReserved4C; // 0x4C + uint8_t RegPaDac; // 0x4D + uint8_t RegTestReserved4E[0x5B - 0x4E]; // 0x4E-0x5A + uint8_t RegFormerTemp; // 0x5B + uint8_t RegTestReserved5C[0x61 - 0x5C]; // 0x5C-0x60 + // Additional settings + uint8_t RegAgcRef; // 0x61 + uint8_t RegAgcThresh1; // 0x62 + uint8_t RegAgcThresh2; // 0x63 + uint8_t RegAgcThresh3; // 0x64 + uint8_t RegTestReserved65[0x70 - 0x65]; // 0x65-0x6F + uint8_t RegPll; // 0x70 +}tSX1276LR; + +extern tSX1276LR* SX1276LR; + +/*! + * \brief Initializes the SX1276 + */ +void SX1276LoRaInit( void ); + +/*! + * \brief Sets the SX1276 to datasheet default values + */ +void SX1276LoRaSetDefaults( void ); + +/*! + * \brief Enables/Disables the LoRa modem + * + * \param [IN]: enable [true, false] + */ +void SX1276LoRaSetLoRaOn( bool enable ); + +/*! + * \brief Sets the SX1276 operating mode + * + * \param [IN] opMode New operating mode + */ +void SX1276LoRaSetOpMode( uint8_t opMode ); + +/*! + * \brief Gets the SX1276 operating mode + * + * \retval opMode Current operating mode + */ +uint8_t SX1276LoRaGetOpMode( void ); + +/*! + * \brief Reads the current Rx gain setting + * + * \retval rxGain Current gain setting + */ +uint8_t SX1276LoRaReadRxGain( void ); + +/*! + * \brief Trigs and reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ +double SX1276LoRaReadRssi( void ); + +/*! + * \brief Gets the Rx gain value measured while receiving the packet + * + * \retval rxGainValue Current Rx gain value + */ +uint8_t SX1276LoRaGetPacketRxGain( void ); + +/*! + * \brief Gets the SNR value measured while receiving the packet + * + * \retval snrValue Current SNR value in [dB] + */ +int8_t SX1276LoRaGetPacketSnr( void ); + +/*! + * \brief Gets the RSSI value measured while receiving the packet + * + * \retval rssiValue Current RSSI value in [dBm] + */ +double SX1276LoRaGetPacketRssi( void ); + +/*! + * \brief Sets the radio in Rx mode. Waiting for a packet + */ +void SX1276LoRaStartRx( void ); + +/*! + * \brief Gets a copy of the current received buffer + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void SX1276LoRaGetRxPacket( void *buffer, uint16_t *size ); + +/*! + * \brief Sets a copy of the buffer to be transmitted + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void SX1276LoRaSetTxPacket( const void *buffer, uint16_t size ); + +/*! + * \brief Gets the current RFState + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +tRFLRStates SX1276LoRaGetRFState( void ); + +/*! + * \brief Sets the new state of the RF state machine + * + * \param [IN]: state New RF state machine state + */ +void SX1276LoRaSetRFState( tRFLRStates state ); + +/*! + * \brief Process the LoRa modem Rx and Tx state machines depending on the + * SX1276 operating mode. + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +uint32_t SX1276LoRaProcess( void ); + +#endif //__SX1276_LORA_H__ \ No newline at end of file