1306 lines
49 KiB
C
1306 lines
49 KiB
C
////////////////////////////////////////////////////////////////////////////////
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// 版权: Haybin.Wu@studio
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// 文件名:
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// 版本： V1.0
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// 工作环境: IAR v6.20
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// 作者: Haybin
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// 生成日期: 2016.05
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// 功能: API
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// 修改日志：
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////////////////////////////////////////////////////////////////////////////////
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// Modify by Qian Xianghong
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// 修改日志：
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// 2020.10
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// 1. LSD_RF_SendPacket()函数:
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// 修改判断DIO0标志的条件，确保发送完成，调用函数无需延时。
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// 前导码长度修改为8.（默认值，和中继器一致）
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// 2. LSD_RF_RXmode()函数:
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// 允许PayloadCrcError中断。
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// 前导码长度修改为8.（默认值，和中继器一致）
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// 3. LSD_RF_RxVariPacket()函数:
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// 判断RxDone和PayloadCRCError标识。
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// 先读取REG_LR_FIFORXCURRENTADDR寄存器的值，再从该地址开始读取数据。
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// 4. LSD_RF_RxFixiPacket()函数:
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// 判断RxDone和PayloadCRCError标识。
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// 5. 增加SX127x_initLora()函数，用于更灵活地初始化LoRa参数。
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//
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//2021.05
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// 1. SX127x_initLora()函数:
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// 打开PayloadCrc校验。
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// 2. LSD_RF_RxVariPacket()函数:
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// 增加判断Crc是否启用。
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// 3. LSD_RF_RxFixiPacket()函数:
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// 增加判断Crc是否启用。
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//
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////////////////////////////////////////////////////////////////////////////////
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#include <stdbool.h>
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#include <stdint.h>
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#include "FR2433-RFSX.h"
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#ifndef RF_SX1276
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#define RF_SX1276
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uint8_t LSD_RF_FreqSet(uint8_t ch);
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uint8_t LSD_RF_PoutSet(uint8_t power);
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//===================================定义===================================================
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#define RF_PAYLOAD_LEN (64)
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#pragma pack(push, 1)
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// LORA参数，和泽耀参数类似
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typedef struct
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{
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uint8_t sof; // 前导码，固定为0xC2
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uint16_t addr; // 通信地址
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unsigned char sf : 3; // 扩频因子: 0-保留，1-7,...,6-12,7-保留
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unsigned char baud : 3; // 串口波特率：3-9600,7-115200, 其余保留
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unsigned char cr : 2; // 编码率: 0-4/5,1-4/6,2-4/7,3-4/8
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uint8_t ch; // 通信信道: 0~40(470M~510M),其余保留
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unsigned char power : 2; // Power: 0-20dBm,1-17dBm,2-14dBm,3-11dBm
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unsigned char freqcast: 1; // 是否指定信道发送
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unsigned char bw : 4; // 0-7.8kHz,1-10.4kHz,...,9-500kHz, 其余保留
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unsigned char unicast : 1; // 是否定点发送
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} lora_param_t;
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#pragma pack(pop)
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//===================================定义===================================================
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/*!
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* SX1276 LoRa General parameters definition
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*/
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typedef struct sLoRaSettings
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{
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uint32_t RFFrequency;
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int8_t Power;
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uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz,
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// 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved]
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uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips]
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uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
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bool CrcOn; // [0: OFF, 1: ON]
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bool ImplicitHeaderOn; // [0: OFF, 1: ON]
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bool RxSingleOn; // [0: Continuous, 1 Single]
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bool FreqHopOn; // [0: OFF, 1: ON]
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uint8_t HopPeriod; // Hops every frequency hopping period symbols
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uint32_t TxPacketTimeout;
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uint32_t RxPacketTimeout;
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uint8_t PayloadLength;
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}tLoRaSettings;
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/*!
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* RF packet definition
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*/
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#define RF_BUFFER_SIZE_MAX 128
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#define RF_BUFFER_SIZE 80
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/*!
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* RF state machine
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*/
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//LoRa
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typedef enum
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{
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RFLR_STATE_IDLE,
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RFLR_STATE_RX_INIT,
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RFLR_STATE_RX_RUNNING,
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RFLR_STATE_RX_DONE,
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RFLR_STATE_RX_TIMEOUT,
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RFLR_STATE_TX_INIT,
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RFLR_STATE_TX_RUNNING,
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RFLR_STATE_TX_DONE,
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RFLR_STATE_TX_TIMEOUT,
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RFLR_STATE_CAD_INIT,
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RFLR_STATE_CAD_RUNNING,
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}tRFLRStates;
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/*!
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* SX1276 definitions
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*/
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#define XTAL_FREQ 32000000
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#define FREQ_STEP 61.03515625
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/*!
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* SX1276 Internal registers Address
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*/
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#define REG_LR_FIFO 0x00
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// Common settings
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#define REG_LR_OPMODE 0x01
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//#define REG_LR_BANDSETTING 0x04
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#define REG_LR_FRFMSB 0x06
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#define REG_LR_FRFMID 0x07
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#define REG_LR_FRFLSB 0x08
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// Tx settings
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#define REG_LR_PACONFIG 0x09
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#define REG_LR_PARAMP 0x0A
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#define REG_LR_OCP 0x0B
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// Rx settings
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#define REG_LR_LNA 0x0C
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// LoRa registers
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#define REG_LR_FIFOADDRPTR 0x0D
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#define REG_LR_FIFOTXBASEADDR 0x0E
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#define REG_LR_FIFORXBASEADDR 0x0F
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#define REG_LR_FIFORXCURRENTADDR 0x10
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#define REG_LR_IRQFLAGSMASK 0x11
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#define REG_LR_IRQFLAGS 0x12
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#define REG_LR_NBRXBYTES 0x13
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#define REG_LR_RXHEADERCNTVALUEMSB 0x14
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#define REG_LR_RXHEADERCNTVALUELSB 0x15
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#define REG_LR_RXPACKETCNTVALUEMSB 0x16
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#define REG_LR_RXPACKETCNTVALUELSB 0x17
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#define REG_LR_MODEMSTAT 0x18
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#define REG_LR_PKTSNRVALUE 0x19
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#define REG_LR_PKTRSSIVALUE 0x1A
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#define REG_LR_RSSIVALUE 0x1B
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#define REG_LR_HOPCHANNEL 0x1C
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#define REG_LR_MODEMCONFIG1 0x1D
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#define REG_LR_MODEMCONFIG2 0x1E
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#define REG_LR_SYMBTIMEOUTLSB 0x1F
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#define REG_LR_PREAMBLEMSB 0x20
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#define REG_LR_PREAMBLELSB 0x21
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#define REG_LR_PAYLOADLENGTH 0x22
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#define REG_LR_PAYLOADMAXLENGTH 0x23
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#define REG_LR_HOPPERIOD 0x24
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#define REG_LR_FIFORXBYTEADDR 0x25
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#define REG_LR_MODEMCONFIG3 0x26
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// end of documented register in datasheet
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// I/O settings
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#define REG_LR_DIOMAPPING1 0x40
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#define REG_LR_DIOMAPPING2 0x41
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// Version
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#define REG_LR_VERSION 0x42
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// Additional settings
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#define REG_LR_PLLHOP 0x44
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#define REG_LR_TCXO 0x4B
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#define REG_LR_PADAC 0x4D
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#define REG_LR_FORMERTEMP 0x5B
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#define REG_LR_BITRATEFRAC 0x5D
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#define REG_LR_AGCREF 0x61
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#define REG_LR_AGCTHRESH1 0x62
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#define REG_LR_AGCTHRESH2 0x63
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#define REG_LR_AGCTHRESH3 0x64
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/*!
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* SX1276 LoRa bit control definition
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*/
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/*!
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* RegFifo
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*/
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/*!
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* RegOpMode
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*/
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#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
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#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
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#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
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#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
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#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
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#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
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#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7
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#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default
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#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00
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#define RFLR_OPMODE_MASK 0xF8
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#define RFLR_OPMODE_SLEEP 0x00
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#define RFLR_OPMODE_STANDBY 0x01 // Default
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#define RFLR_OPMODE_SYNTHESIZER_TX 0x02
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#define RFLR_OPMODE_TRANSMITTER 0x03
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#define RFLR_OPMODE_SYNTHESIZER_RX 0x04
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#define RFLR_OPMODE_RECEIVER 0x05
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// LoRa specific modes
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#define RFLR_OPMODE_RECEIVER_SINGLE 0x06
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#define RFLR_OPMODE_CAD 0x07
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/*!
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* RegBandSetting
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*/
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#define RFLR_BANDSETTING_MASK 0x3F
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#define RFLR_BANDSETTING_AUTO 0x00 // Default
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#define RFLR_BANDSETTING_DIV_BY_1 0x40
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#define RFLR_BANDSETTING_DIV_BY_2 0x80
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#define RFLR_BANDSETTING_DIV_BY_6 0xC0
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/*!
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* RegPaConfig
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*/
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#define RFLR_PACONFIG_PASELECT_MASK 0x7F
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#define RFLR_PACONFIG_PASELECT_PABOOST 0x80
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#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
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#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F
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#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
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/*!
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* RegPaRamp
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*/
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#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF
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#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10
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#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default
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#define RFLR_PARAMP_MASK 0xF0
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#define RFLR_PARAMP_3400_US 0x00
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#define RFLR_PARAMP_2000_US 0x01
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#define RFLR_PARAMP_1000_US 0x02
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#define RFLR_PARAMP_0500_US 0x03
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#define RFLR_PARAMP_0250_US 0x04
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#define RFLR_PARAMP_0125_US 0x05
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#define RFLR_PARAMP_0100_US 0x06
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#define RFLR_PARAMP_0062_US 0x07
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#define RFLR_PARAMP_0050_US 0x08
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#define RFLR_PARAMP_0040_US 0x09 // Default
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#define RFLR_PARAMP_0031_US 0x0A
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#define RFLR_PARAMP_0025_US 0x0B
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#define RFLR_PARAMP_0020_US 0x0C
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#define RFLR_PARAMP_0015_US 0x0D
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#define RFLR_PARAMP_0012_US 0x0E
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#define RFLR_PARAMP_0010_US 0x0F
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/*!
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* RegOcp
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*/
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#define RFLR_OCP_MASK 0xDF
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#define RFLR_OCP_ON 0x20 // Default
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#define RFLR_OCP_OFF 0x00
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#define RFLR_OCP_TRIM_MASK 0xE0
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#define RFLR_OCP_TRIM_045_MA 0x00
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#define RFLR_OCP_TRIM_050_MA 0x01
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#define RFLR_OCP_TRIM_055_MA 0x02
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#define RFLR_OCP_TRIM_060_MA 0x03
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#define RFLR_OCP_TRIM_065_MA 0x04
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#define RFLR_OCP_TRIM_070_MA 0x05
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#define RFLR_OCP_TRIM_075_MA 0x06
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#define RFLR_OCP_TRIM_080_MA 0x07
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#define RFLR_OCP_TRIM_085_MA 0x08
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#define RFLR_OCP_TRIM_090_MA 0x09
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#define RFLR_OCP_TRIM_095_MA 0x0A
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#define RFLR_OCP_TRIM_100_MA 0x0B // Default
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#define RFLR_OCP_TRIM_105_MA 0x0C
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#define RFLR_OCP_TRIM_110_MA 0x0D
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#define RFLR_OCP_TRIM_115_MA 0x0E
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#define RFLR_OCP_TRIM_120_MA 0x0F
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#define RFLR_OCP_TRIM_130_MA 0x10
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#define RFLR_OCP_TRIM_140_MA 0x11
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#define RFLR_OCP_TRIM_150_MA 0x12
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#define RFLR_OCP_TRIM_160_MA 0x13
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#define RFLR_OCP_TRIM_170_MA 0x14
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#define RFLR_OCP_TRIM_180_MA 0x15
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#define RFLR_OCP_TRIM_190_MA 0x16
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#define RFLR_OCP_TRIM_200_MA 0x17
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#define RFLR_OCP_TRIM_210_MA 0x18
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#define RFLR_OCP_TRIM_220_MA 0x19
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#define RFLR_OCP_TRIM_230_MA 0x1A
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#define RFLR_OCP_TRIM_240_MA 0x1B
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/*!
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* RegLna
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*/
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#define RFLR_LNA_GAIN_MASK 0x1F
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#define RFLR_LNA_GAIN_G1 0x20 // Default
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#define RFLR_LNA_GAIN_G2 0x40
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#define RFLR_LNA_GAIN_G3 0x60
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#define RFLR_LNA_GAIN_G4 0x80
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#define RFLR_LNA_GAIN_G5 0xA0
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#define RFLR_LNA_GAIN_G6 0xC0
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#define RFLR_LNA_BOOST_LF_MASK 0xE7
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#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default
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#define RFLR_LNA_BOOST_LF_GAIN 0x08
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#define RFLR_LNA_BOOST_LF_IP3 0x10
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#define RFLR_LNA_BOOST_LF_BOOST 0x18
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#define RFLR_LNA_RXBANDFORCE_MASK 0xFB
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#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04
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#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default
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#define RFLR_LNA_BOOST_HF_MASK 0xFC
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#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default
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#define RFLR_LNA_BOOST_HF_ON 0x03
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/*!
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* RegFifoAddrPtr
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*/
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#define RFLR_FIFOADDRPTR 0x00 // Default
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/*!
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* RegFifoTxBaseAddr
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*/
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#define RFLR_FIFOTXBASEADDR 0x80 // Default
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/*!
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* RegFifoTxBaseAddr
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*/
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#define RFLR_FIFORXBASEADDR 0x00 // Default
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/*!
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* RegFifoRxCurrentAddr (Read Only)
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*/
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/*!
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* RegIrqFlagsMask
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*/
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#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
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#define RFLR_IRQFLAGS_RXDONE_MASK 0x40
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#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
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#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
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#define RFLR_IRQFLAGS_TXDONE_MASK 0x08
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#define RFLR_IRQFLAGS_CADDONE_MASK 0x04
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#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
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#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
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/*!
|
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* RegIrqFlags
|
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*/
|
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#define RFLR_IRQFLAGS_RXTIMEOUT 0x80
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#define RFLR_IRQFLAGS_RXDONE 0x40
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#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
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#define RFLR_IRQFLAGS_VALIDHEADER 0x10
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#define RFLR_IRQFLAGS_TXDONE 0x08
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#define RFLR_IRQFLAGS_CADDONE 0x04
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#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
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#define RFLR_IRQFLAGS_CADDETECTED 0x01
|
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||
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|
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/*!
|
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* RegFifoRxNbBytes (Read Only) //
|
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*/
|
||
|
||
|
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/*!
|
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* RegRxHeaderCntValueMsb (Read Only) //
|
||
*/
|
||
|
||
|
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/*!
|
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* RegRxHeaderCntValueLsb (Read Only) //
|
||
*/
|
||
|
||
|
||
/*!
|
||
* RegRxPacketCntValueMsb (Read Only) //
|
||
*/
|
||
|
||
|
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/*!
|
||
* RegRxPacketCntValueLsb (Read Only) //
|
||
*/
|
||
|
||
|
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/*!
|
||
* RegModemStat (Read Only) //
|
||
*/
|
||
#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
|
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#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
|
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|
||
/*!
|
||
* RegPktSnrValue (Read Only) //
|
||
*/
|
||
|
||
|
||
/*!
|
||
* RegPktRssiValue (Read Only) //
|
||
*/
|
||
|
||
|
||
/*!
|
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* RegRssiValue (Read Only) //
|
||
*/
|
||
|
||
|
||
/*!
|
||
* RegModemConfig1
|
||
*/
|
||
#define RFLR_MODEMCONFIG1_BW_MASK 0x0F
|
||
|
||
#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00
|
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#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10
|
||
#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20
|
||
#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30
|
||
#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40
|
||
#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50
|
||
#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60
|
||
#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default
|
||
#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80
|
||
#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90
|
||
#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1
|
||
#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02
|
||
#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default
|
||
#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06
|
||
#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08
|
||
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE
|
||
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01
|
||
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
|
||
|
||
/*!
|
||
* RegModemConfig2
|
||
*/
|
||
#define RFLR_MODEMCONFIG2_SF_MASK 0x0F
|
||
#define RFLR_MODEMCONFIG2_SF_6 0x60
|
||
#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
|
||
#define RFLR_MODEMCONFIG2_SF_8 0x80
|
||
#define RFLR_MODEMCONFIG2_SF_9 0x90
|
||
#define RFLR_MODEMCONFIG2_SF_10 0xA0
|
||
#define RFLR_MODEMCONFIG2_SF_11 0xB0
|
||
#define RFLR_MODEMCONFIG2_SF_12 0xC0
|
||
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
|
||
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
|
||
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
|
||
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB
|
||
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04
|
||
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default
|
||
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
|
||
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
|
||
|
||
|
||
/*!
|
||
* RegHopChannel (Read Only)
|
||
*/
|
||
|
||
#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
|
||
#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
|
||
#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
|
||
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF
|
||
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40
|
||
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default
|
||
#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
|
||
|
||
|
||
/*!
|
||
* RegSymbTimeoutLsb
|
||
*/
|
||
#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
|
||
|
||
/*!
|
||
* RegPreambleLengthMsb
|
||
*/
|
||
#define RFLR_PREAMBLELENGTHMSB 0x00 // Default
|
||
|
||
/*!
|
||
* RegPreambleLengthLsb
|
||
*/
|
||
#define RFLR_PREAMBLELENGTHLSB 0x08 // Default
|
||
|
||
/*!
|
||
* RegPayloadLength
|
||
*/
|
||
#define RFLR_PAYLOADLENGTH 0x0E // Default
|
||
|
||
/*!
|
||
* RegPayloadMaxLength
|
||
*/
|
||
#define RFLR_PAYLOADMAXLENGTH 0xFF // Default
|
||
|
||
/*!
|
||
* RegHopPeriod
|
||
*/
|
||
#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
|
||
|
||
|
||
/*!
|
||
* RegDioMapping1
|
||
*/
|
||
#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
|
||
#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
|
||
#define RFLR_DIOMAPPING1_DIO0_01 0x40
|
||
#define RFLR_DIOMAPPING1_DIO0_10 0x80
|
||
#define RFLR_DIOMAPPING1_DIO0_11 0xC0
|
||
|
||
#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
|
||
#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
|
||
#define RFLR_DIOMAPPING1_DIO1_01 0x10
|
||
#define RFLR_DIOMAPPING1_DIO1_10 0x20
|
||
#define RFLR_DIOMAPPING1_DIO1_11 0x30
|
||
|
||
#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
|
||
#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
|
||
#define RFLR_DIOMAPPING1_DIO2_01 0x04
|
||
#define RFLR_DIOMAPPING1_DIO2_10 0x08
|
||
#define RFLR_DIOMAPPING1_DIO2_11 0x0C
|
||
|
||
#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
|
||
#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
|
||
#define RFLR_DIOMAPPING1_DIO3_01 0x01
|
||
#define RFLR_DIOMAPPING1_DIO3_10 0x02
|
||
#define RFLR_DIOMAPPING1_DIO3_11 0x03
|
||
|
||
/*!
|
||
* RegDioMapping2
|
||
*/
|
||
#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
|
||
#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
|
||
#define RFLR_DIOMAPPING2_DIO4_01 0x40
|
||
#define RFLR_DIOMAPPING2_DIO4_10 0x80
|
||
#define RFLR_DIOMAPPING2_DIO4_11 0xC0
|
||
|
||
#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
|
||
#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
|
||
#define RFLR_DIOMAPPING2_DIO5_01 0x10
|
||
#define RFLR_DIOMAPPING2_DIO5_10 0x20
|
||
#define RFLR_DIOMAPPING2_DIO5_11 0x30
|
||
|
||
#define RFLR_DIOMAPPING2_MAP_MASK 0xFE
|
||
#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
|
||
#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
|
||
|
||
/*!
|
||
* RegVersion (Read Only)
|
||
*/
|
||
|
||
/*!
|
||
* RegAgcRef
|
||
*/
|
||
|
||
/*!
|
||
* RegAgcThresh1
|
||
*/
|
||
|
||
/*!
|
||
* RegAgcThresh2
|
||
*/
|
||
|
||
/*!
|
||
* RegAgcThresh3
|
||
*/
|
||
|
||
/*!
|
||
* RegFifoRxByteAddr (Read Only)
|
||
*/
|
||
|
||
/*!
|
||
* RegPllHop
|
||
*/
|
||
#define RFLR_PLLHOP_FASTHOP_MASK 0x7F
|
||
#define RFLR_PLLHOP_FASTHOP_ON 0x80
|
||
#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
|
||
|
||
/*!
|
||
* RegTcxo
|
||
*/
|
||
#define RFLR_TCXO_TCXOINPUT_MASK 0xEF
|
||
#define RFLR_TCXO_TCXOINPUT_ON 0x10
|
||
#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
|
||
|
||
/*!
|
||
* RegPaDac
|
||
*/
|
||
#define RFLR_PADAC_20DBM_MASK 0xF8
|
||
#define RFLR_PADAC_20DBM_ON 0x07
|
||
#define RFLR_PADAC_20DBM_OFF 0x04 // Default
|
||
|
||
/*!
|
||
* RegPll
|
||
*/
|
||
#define RFLR_PLL_BANDWIDTH_MASK 0x3F
|
||
#define RFLR_PLL_BANDWIDTH_75 0x00
|
||
#define RFLR_PLL_BANDWIDTH_150 0x40
|
||
#define RFLR_PLL_BANDWIDTH_225 0x80
|
||
#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
|
||
|
||
/*!
|
||
* RegPllLowPn
|
||
*/
|
||
#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
|
||
#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
|
||
#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
|
||
#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
|
||
#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
|
||
|
||
/*!
|
||
* RegModemConfig3
|
||
*/
|
||
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7
|
||
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08
|
||
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
|
||
|
||
#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB
|
||
#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default
|
||
#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00
|
||
|
||
/*!
|
||
* RegFormerTemp
|
||
*/
|
||
|
||
typedef struct sSX1276LR
|
||
{
|
||
uint8_t RegFifo; // 0x00
|
||
// Common settings
|
||
uint8_t RegOpMode; // 0x01
|
||
|
||
uint8_t RegTestReserved02[0x06 - 0x02]; // 0x02-0x05
|
||
// uint8_t RegRes02; // 0x02
|
||
// uint8_t RegRes03; // 0x03
|
||
// uint8_t RegBandSetting; // 0x04
|
||
// uint8_t RegRes05; // 0x05
|
||
|
||
uint8_t RegFrfMsb; // 0x06
|
||
uint8_t RegFrfMid; // 0x07
|
||
uint8_t RegFrfLsb; // 0x08
|
||
// Tx settings
|
||
uint8_t RegPaConfig; // 0x09
|
||
uint8_t RegPaRamp; // 0x0A
|
||
uint8_t RegOcp; // 0x0B
|
||
// Rx settings
|
||
uint8_t RegLna; // 0x0C
|
||
// LoRa registers
|
||
uint8_t RegFifoAddrPtr; // 0x0D
|
||
uint8_t RegFifoTxBaseAddr; // 0x0E
|
||
uint8_t RegFifoRxBaseAddr; // 0x0F
|
||
uint8_t RegFifoRxCurrentAddr; // 0x10
|
||
uint8_t RegIrqFlagsMask; // 0x11
|
||
uint8_t RegIrqFlags; // 0x12
|
||
uint8_t RegNbRxBytes; // 0x13
|
||
uint8_t RegRxHeaderCntValueMsb; // 0x14
|
||
uint8_t RegRxHeaderCntValueLsb; // 0x15
|
||
uint8_t RegRxPacketCntValueMsb; // 0x16
|
||
uint8_t RegRxPacketCntValueLsb; // 0x17
|
||
uint8_t RegModemStat; // 0x18
|
||
uint8_t RegPktSnrValue; // 0x19
|
||
uint8_t RegPktRssiValue; // 0x1A
|
||
uint8_t RegRssiValue; // 0x1B
|
||
uint8_t RegHopChannel; // 0x1C
|
||
uint8_t RegModemConfig1; // 0x1D
|
||
uint8_t RegModemConfig2; // 0x1E
|
||
uint8_t RegSymbTimeoutLsb; // 0x1F
|
||
uint8_t RegPreambleMsb; // 0x20
|
||
uint8_t RegPreambleLsb; // 0x21
|
||
uint8_t RegPayloadLength; // 0x22
|
||
uint8_t RegMaxPayloadLength; // 0x23
|
||
uint8_t RegHopPeriod; // 0x24
|
||
uint8_t RegFifoRxByteAddr; // 0x25
|
||
uint8_t RegModemConfig3; // 0x26
|
||
uint8_t RegTestReserved27[0x31 - 0x27]; // 0x27-0x30
|
||
//void SX1276LoRaSetNbTrigPeaks( uint8_t value )用到
|
||
uint8_t RegTestReserved31; // 0x31
|
||
uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x3F
|
||
// I/O settings
|
||
uint8_t RegDioMapping1; // 0x40
|
||
uint8_t RegDioMapping2; // 0x41
|
||
// Version
|
||
uint8_t RegVersion; // 0x42
|
||
|
||
uint8_t RegTestReserved43[0x4B - 0x43]; // 0x43-0x4A
|
||
uint8_t RegTcxo; // 0x4B
|
||
uint8_t RegTestReserved4C; // 0x4C
|
||
uint8_t RegPaDac; // 0x4D
|
||
uint8_t RegTestReserved4E[0x5B - 0x4E]; // 0x4E-0x5A
|
||
uint8_t RegFormerTemp; // 0x5B
|
||
uint8_t RegTestReserved5C[0x61 - 0x5C]; // 0x5C-0x60
|
||
// Additional settings
|
||
uint8_t RegAgcRef; // 0x61
|
||
uint8_t RegAgcThresh1; // 0x62
|
||
uint8_t RegAgcThresh2; // 0x63
|
||
uint8_t RegAgcThresh3; // 0x64
|
||
uint8_t RegTestReserved65[0x70 - 0x65]; // 0x65-0x6F
|
||
uint8_t RegPll; // 0x70
|
||
}tSX1276LR;
|
||
//////////////////////////////////////////////////////////////////////////////
|
||
typedef enum
|
||
{
|
||
Init_LoRa_0_8K,
|
||
Init_LoRa_4_8K,
|
||
Init_LoRa_10k,
|
||
}tSX127xInitPara; //定义速率枚举
|
||
|
||
typedef enum
|
||
{
|
||
NORMAL, //正常
|
||
PARAMETER_INVALID, //参数不可用
|
||
SPI_READCHECK_WRONG, //SPI出错
|
||
}tSX127xError; //定义出错枚举
|
||
|
||
typedef enum
|
||
{
|
||
SLEEP,
|
||
STANDBY,
|
||
TX_ONGOING,
|
||
RX_ONGOING,
|
||
}tSX127xState; //定义RF物理状态，用户可以不使用
|
||
|
||
typedef enum
|
||
{
|
||
HOLDON,
|
||
TX,
|
||
LISTENING,
|
||
}tRadio_Machine; //定义逻辑状态，用户可以不使用
|
||
|
||
typedef enum
|
||
{
|
||
MASTER,
|
||
SLAVE,
|
||
}tMasterSlave; //定义主从枚举 ，测试时用
|
||
|
||
typedef struct
|
||
{
|
||
tMasterSlave MasterSlave; //主从
|
||
tSX127xState SX127xState; //物理状态
|
||
tRadio_Machine Machine; //逻辑状态
|
||
}stRadio_Situation; //定义状态结构体
|
||
|
||
const unsigned char Freq_Cal_Tab[]=
|
||
{
|
||
0x75,0x80,0x00,//470MHz
|
||
0x75,0xC0,0x00,//471MHz
|
||
0x76,0x00,0x00,//472MHz
|
||
0x76,0x40,0x00,//473MHz
|
||
0x76,0x80,0x00,//474MHz
|
||
0x76,0xC0,0x00,//475MHz
|
||
0x77,0x00,0x00,//476MHz
|
||
0x77,0x40,0x00,//477MHz
|
||
0x77,0x80,0x00,//478MHz
|
||
0x77,0xC0,0x00,//479MHz
|
||
0x78,0x00,0x00,//480MHz
|
||
0x78,0x40,0x00,//481MHz
|
||
0x78,0x80,0x00,//482MHz
|
||
0x78,0xC0,0x00,//483MHz
|
||
0x79,0x00,0x00,//484MHz
|
||
0x79,0x40,0x00,//485MHz
|
||
0x79,0x80,0x00,//486MHz
|
||
0x79,0xC0,0x00,//487MHz
|
||
0x7A,0x00,0x00,//488MHz
|
||
0x7A,0x40,0x00,//489MHz
|
||
0x7A,0x80,0x00,//490MHz
|
||
0x7A,0xC0,0x00,//491MHz
|
||
0x7B,0x00,0x00,//492MHz
|
||
0x7B,0x40,0x00,//493MHz
|
||
0x7B,0x80,0x00,//494MHz
|
||
0x7B,0xC0,0x00,//495MHz
|
||
0x7C,0x00,0x00,//496MHz
|
||
0x7C,0x40,0x00,//497MHz
|
||
0x7C,0x80,0x00,//498MHz
|
||
0x7C,0xC0,0x00,//499MHz
|
||
0x7D,0x00,0x00,//500MHz
|
||
0x7D,0x40,0x00,//501MHz
|
||
0x7D,0x80,0x00,//502MHz
|
||
0x7D,0xC0,0x00,//503MHz
|
||
0x7E,0x00,0x00,//504MHz
|
||
0x7E,0x40,0x00,//505MHz
|
||
0x7E,0x80,0x00,//506MHz
|
||
0x7E,0xC0,0x00,//507MHz
|
||
0x7F,0x00,0x00,//508MHz
|
||
0x7F,0x40,0x00,//509MHz
|
||
0x7F,0x80,0x00,//510MHz
|
||
};
|
||
|
||
//extern stRadio_Situation SX127xSituation;
|
||
//===================================函数声明===================================================
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF初始化
|
||
// 输入参数 : tSX127xInitPara initPara 输入速率Init_LoRa_0_8K, Init_LoRa_4_8K , Init_LoRa_10k,
|
||
// 返回参数 : tSX127xError 错误枚举内容
|
||
// 说明 : 初始化时，信道初始化默认为0信道
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
tSX127xError SX127x_init(tSX127xInitPara initPara)
|
||
{
|
||
uint8_t test = 0;
|
||
if(initPara>Init_LoRa_10k) //如果输入参数错误
|
||
{
|
||
return PARAMETER_INVALID; //报错输入
|
||
}
|
||
SX1276Init_IO(); // PAIO口初始化
|
||
SX1276Reset(); //复位RF
|
||
//init Regs
|
||
SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP );
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP );
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_PACONFIG, 0xff );
|
||
SX1276Write( REG_LR_PADAC, RFLR_PADAC_20DBM_ON );
|
||
SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US);
|
||
SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);
|
||
SX1276Write( REG_LR_PAYLOADLENGTH,2);
|
||
SX1276Write( REG_LR_MODEMCONFIG3,\
|
||
RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON|
|
||
RFLR_MODEMCONFIG3_AGCAUTO_ON);
|
||
//BW,SF,CR,Header,CRC
|
||
// SX1276Write( REG_LR_MODEMCONFIG2,0xFF);
|
||
// SX1276Write( REG_LR_SYMBTIMEOUTLSB,0xFF);
|
||
switch(initPara){
|
||
case Init_LoRa_0_8K:
|
||
// SX1276Write( REG_LR_MODEMCONFIG3,\
|
||
// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON|
|
||
// RFLR_MODEMCONFIG3_AGCAUTO_ON);
|
||
|
||
SX1276Write( REG_LR_MODEMCONFIG1,\
|
||
RFLR_MODEMCONFIG1_BW_125_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\
|
||
RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF);
|
||
SX1276Write( REG_LR_MODEMCONFIG2,\
|
||
RFLR_MODEMCONFIG2_SF_9|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON);
|
||
SX1276Write( REG_LR_PREAMBLELSB,10);
|
||
SX1276Write(0x31,0x55);
|
||
SX1276Read( 0x31,&test);
|
||
break;
|
||
case Init_LoRa_4_8K:
|
||
// SX1276Write( REG_LR_MODEMCONFIG3,\
|
||
// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF|
|
||
// RFLR_MODEMCONFIG3_AGCAUTO_OFF);
|
||
|
||
SX1276Write( REG_LR_MODEMCONFIG1,\
|
||
RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\
|
||
RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF);
|
||
SX1276Write( REG_LR_MODEMCONFIG2,\
|
||
RFLR_MODEMCONFIG2_SF_8|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON);
|
||
// SX1276Write( REG_LR_PREAMBLEMSB,1);
|
||
SX1276Write( REG_LR_PREAMBLELSB,10);
|
||
break;
|
||
case Init_LoRa_10k:
|
||
SX1276Read( 0x31,&test);
|
||
SX1276Write( 0x31,(test& 0xF8)|0x05);
|
||
SX1276Write( 0x37,0x0C);
|
||
// SX1276Write( REG_LR_MODEMCONFIG3,\
|
||
// RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF|
|
||
// RFLR_MODEMCONFIG3_AGCAUTO_ON);
|
||
|
||
SX1276Write( REG_LR_MODEMCONFIG1,\
|
||
RFLR_MODEMCONFIG1_BW_500_KHZ+RFLR_MODEMCONFIG1_CODINGRATE_4_8+\
|
||
RFLR_MODEMCONFIG1_IMPLICITHEADER_ON);
|
||
SX1276Write( REG_LR_MODEMCONFIG2,\
|
||
RFLR_MODEMCONFIG2_SF_6|RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON);
|
||
// SX1276Write( REG_LR_PREAMBLEMSB,4);
|
||
SX1276Write( REG_LR_PREAMBLELSB,10);
|
||
break;
|
||
default:
|
||
break;
|
||
}
|
||
if(!LSD_RF_FreqSet(1)) //设置为0信道
|
||
return SPI_READCHECK_WRONG;
|
||
|
||
return NORMAL;
|
||
}
|
||
|
||
//===================================函数声明===================================================
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF初始化
|
||
// 输入参数 : lora_param_t lora 输入参数
|
||
// 返回参数 : tSX127xError 错误枚举内容
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
tSX127xError SX127x_initLora(lora_param_t *lora)
|
||
{
|
||
static uint8_t first = 1;
|
||
|
||
// 检查参数
|
||
if(lora->sof != 0xC2 || lora->sf > 6 || (lora->baud != 3 && lora->baud != 5 && lora->baud != 7) || lora->ch > 40 || lora->bw > 9)
|
||
return PARAMETER_INVALID;
|
||
|
||
if(first)
|
||
{
|
||
first = 0;
|
||
SX1276Init_IO(); // PAIO口初始化
|
||
}
|
||
SX1276Reset(); //复位RF
|
||
|
||
//切换到LoRamode，standby状态
|
||
SX1276Write( REG_LR_OPMODE, RFLR_OPMODE_SLEEP );
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP );
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
|
||
/*------------------------------------------------
|
||
SPI 验证 */
|
||
uint8_t test = 0;
|
||
SX1276Write( REG_LR_HOPPERIOD,0x91 );//选一个用不到的寄存器来做验证
|
||
SX1276Read( REG_LR_HOPPERIOD,&test);
|
||
if(test!=0x91)
|
||
return SPI_READCHECK_WRONG;
|
||
|
||
SX1276Write( REG_LR_PACONFIG, 0xff );
|
||
|
||
//Frequency Configuration
|
||
LSD_RF_FreqSet(lora->ch); //设置频率
|
||
//PA Configuration
|
||
switch(lora->power)
|
||
{
|
||
case 0: // 20dBm
|
||
LSD_RF_PoutSet(15);
|
||
break;
|
||
case 1: // 17dBm
|
||
LSD_RF_PoutSet(15);
|
||
break;
|
||
case 2: // 14dBm
|
||
LSD_RF_PoutSet(12);
|
||
break;
|
||
case 3: // 11dBm
|
||
LSD_RF_PoutSet(9);
|
||
break;
|
||
}
|
||
|
||
SX1276Write( REG_LR_PARAMP,RFLR_PARAMP_1000_US);
|
||
// ↑PA Ramp的时间，如果用户LDO不能快速输出大电流（泵能力），适当增加PA Ramp时间
|
||
// ↑如果Ramp时间过短超过了LDO的能力时，会出现进入TX后，系统电流为发射电流，但是RF信号不出现的现象
|
||
SX1276Write( REG_LR_OCP,0x20|RFLR_OCP_TRIM_240_MA);//电流过载保护 Over Current Protection
|
||
|
||
//PayloadLength 初始化
|
||
SX1276Write( REG_LR_PAYLOADLENGTH, RF_PAYLOAD_LEN);
|
||
//注意，无头模式（Implicit Header）时，必须提前规定好收发双方的PL
|
||
|
||
//BW、CR、ImplictHeader_On (SF6) / Off (SF7~12)
|
||
SX1276Write( REG_LR_MODEMCONFIG1,\
|
||
(((uint8_t)(lora->bw << 4)) | ((uint8_t) ((lora->cr + 1) << 1))) | (lora->sf == 0 ? 0x01 : 0x00));
|
||
|
||
//SF、PayloadCrc_On
|
||
SX1276Write( REG_LR_MODEMCONFIG2,\
|
||
((uint8_t)((lora->sf + 6) << 4)) | 0x04);
|
||
|
||
uint8_t temp = 0;
|
||
SX1276Read( 0x31,&temp);
|
||
if(0 == lora->sf) //慎用SF = 6，需要的配置很特殊
|
||
{
|
||
SX1276Write( 0x31,(temp& 0xF8)|0x05);
|
||
SX1276Write( 0x37,0x0C);
|
||
}
|
||
else
|
||
{
|
||
SX1276Write( 0x31,(temp& 0xF8)|0x03);
|
||
SX1276Write( 0x37,0x0A);
|
||
}
|
||
|
||
//低速率优化功能是否开启、AutoAGC默认开启
|
||
// 在SF12和500kHz下，必须开启，否则误码率很高
|
||
SX1276Write( REG_LR_MODEMCONFIG3,(\
|
||
RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON\
|
||
)|RFLR_MODEMCONFIG3_AGCAUTO_ON);
|
||
|
||
// 高频开关选项
|
||
SX1276Write( REG_LR_DIOMAPPING2, RFLR_DIOMAPPING2_DIO4_01);
|
||
|
||
return NORMAL;
|
||
}
|
||
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF发送数据包
|
||
// 输入参数 : uint8_t*data：发送数据指针，uint8_t size发送数据长度
|
||
// 返回参数 : 无
|
||
// 说明 : 设置为发送是， preamble改回默认值
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void SX1276_TxPacket(uint8_t*data,uint8_t size)
|
||
{
|
||
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_PREAMBLEMSB,0);
|
||
SX1276Write( REG_LR_PREAMBLELSB,8);
|
||
SX1276Write( REG_LR_PAYLOADLENGTH,size);
|
||
SX1276WriteRxTx(true);
|
||
SX1276Write( REG_LR_FIFOADDRPTR,0x80);
|
||
SX1276WriteBuffer(REG_LR_FIFO,data,size);
|
||
SX1276Write(REG_LR_IRQFLAGS,0xff);
|
||
SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE_MASK));
|
||
SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 );
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER );
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF进入接收状态
|
||
// 输入参数 : uint8_t clen 可变数据包下此值无效，固定数据包为长度值
|
||
// 返回参数 : 无
|
||
// 说明 : 进入接收后preamble设置回默认值为
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void Rx_mode(uint8_t clen)
|
||
{
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_PREAMBLEMSB,0);
|
||
SX1276Write( REG_LR_PREAMBLELSB,8);
|
||
SX1276Write( REG_LR_PAYLOADLENGTH,clen);
|
||
SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE_MASK | RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK));
|
||
SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 );
|
||
SX1276WriteRxTx(false);
|
||
SX1276Write( REG_LR_FIFOADDRPTR,0x00);
|
||
SX1276Write(REG_LR_IRQFLAGS,0xff);
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER );
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF接收可变数据包
|
||
// 输入参数 : uint8_t*cbuf接收数组指针,uint8_t *csize返回长度指针
|
||
// 返回参数 : 无
|
||
// 说明 :
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_RxVariPacket(uint8_t*cbuf,uint8_t *csize)
|
||
{
|
||
uint8_t flag, hop, ptr;
|
||
|
||
SX1276Read(REG_LR_IRQFLAGS, &flag);
|
||
SX1276Read(REG_LR_HOPCHANNEL, &hop);
|
||
|
||
SX1276Read(REG_LR_FIFORXCURRENTADDR, &ptr);
|
||
SX1276Read(REG_LR_NBRXBYTES,csize);
|
||
SX1276Write( REG_LR_FIFOADDRPTR,ptr);
|
||
SX1276ReadFifo(cbuf,*csize);
|
||
|
||
SX1276Write(REG_LR_IRQFLAGS,0xff);
|
||
if(!(flag & RFLR_IRQFLAGS_RXDONE) || ((hop & RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON) && (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR)))
|
||
*csize = 0;
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF接收固定数据包
|
||
// 输入参数 : uint8_t*cbuf接收数组指针,uint8_t csize接收固定长度
|
||
// 返回参数 : 无
|
||
// 说明 : 在速率10k时只能采用固定数据包长度
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_RxFixiPacket(uint8_t*cbuf,uint8_t *csize)
|
||
{
|
||
uint8_t flag, hop;
|
||
|
||
SX1276Read(REG_LR_IRQFLAGS, &flag);
|
||
SX1276Read(REG_LR_HOPCHANNEL, &hop);
|
||
|
||
SX1276Write( REG_LR_FIFOADDRPTR,0x00);
|
||
SX1276ReadFifo(cbuf,*csize);
|
||
|
||
SX1276Write(REG_LR_IRQFLAGS,0xff);
|
||
if(!(flag & RFLR_IRQFLAGS_RXDONE) || ((hop & RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON) && (flag & RFLR_IRQFLAGS_PAYLOADCRCERROR)))
|
||
*csize = 0;
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF进入standby状态
|
||
// 输入参数 : 无
|
||
// 返回参数 : 无
|
||
// 说明 :
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_StandbyMode(void)
|
||
{
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF进入不同信道
|
||
// 输入参数 : uint8_t ch 范围0-40
|
||
// 返回参数 : 无
|
||
// 说明 :
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
uint8_t LSD_RF_FreqSet(uint8_t ch)
|
||
{
|
||
uint8_t test_FRFMSB = 0,test_FRFMID=0,test_FRFLSB=0;
|
||
#if 0
|
||
SX1276Write( REG_LR_FRFMSB,Freq_Cal_Tab[3*ch]);
|
||
SX1276Write( REG_LR_FRFMID,Freq_Cal_Tab[3*ch+1]);
|
||
SX1276Write( REG_LR_FRFLSB,Freq_Cal_Tab[3*ch+2]);
|
||
|
||
SX1276Read(REG_LR_FRFMSB,&test_FRFMSB);
|
||
SX1276Read(REG_LR_FRFMID,&test_FRFMID);
|
||
SX1276Read(REG_LR_FRFLSB,&test_FRFLSB);
|
||
|
||
if(test_FRFMSB !=Freq_Cal_Tab[3*ch])
|
||
return 0;
|
||
if(test_FRFMID !=Freq_Cal_Tab[3*ch+1])
|
||
return 0;
|
||
if(test_FRFLSB !=Freq_Cal_Tab[3*ch+2])
|
||
return 0;
|
||
#else
|
||
const uint32_t FXOSC = 32000000ul;
|
||
float fstep = FXOSC / 524288.0;
|
||
uint32_t freq = 470000000ul + ch * 1000000ul;
|
||
uint32_t frf = (uint32_t) (freq / fstep + 0.5);
|
||
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_FRFMSB, (frf >> 16) & 0xFF);
|
||
SX1276Write( REG_LR_FRFMID, (frf >> 8) & 0xFF);
|
||
SX1276Write( REG_LR_FRFLSB, (frf & 0xff));
|
||
|
||
SX1276Read(REG_LR_FRFMSB,&test_FRFMSB);
|
||
SX1276Read(REG_LR_FRFMID,&test_FRFMID);
|
||
SX1276Read(REG_LR_FRFLSB,&test_FRFLSB);
|
||
|
||
if(test_FRFMSB != ((frf >> 16) & 0xFF))
|
||
return 0;
|
||
if(test_FRFMID != ((frf >> 8) & 0xFF))
|
||
return 0;
|
||
if(test_FRFLSB != (frf & 0xff))
|
||
return 0;
|
||
#endif
|
||
|
||
return 1;
|
||
}
|
||
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF配置功率
|
||
// 输入参数 : 无
|
||
// 返回参数 : 无
|
||
// 说明 :
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
uint8_t LSD_RF_PoutSet(uint8_t power)
|
||
{
|
||
LSD_RF_StandbyMode();
|
||
SX1276Write( REG_LR_PACONFIG, 0xf0|power);
|
||
uint8_t test = 0;
|
||
SX1276Read(REG_LR_PACONFIG,&test);
|
||
if((0xf0|power)!=test)
|
||
return 0;
|
||
SX1276Write( REG_LR_PADAC, 0x80|RFLR_PADAC_20DBM_ON );
|
||
return 1;
|
||
}
|
||
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF发送数据包
|
||
// 输入参数 : uint8_t*data：发送数据指针，uint8_t size发送数据长度
|
||
// 返回参数 : 无
|
||
// 说明 : 数据发送完成后DIO0从低电平变成高电平，每次调用此函数，会自动先将DIO0变为低，等待高电平
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_SendPacket(uint8_t*cbuf,uint8_t csize)
|
||
{
|
||
unsigned long int j=0xFFFFFF; //超时用，用户需要根据实际情况来调整
|
||
DIO0_IFG_L; //清除DIO0标志位
|
||
DIO0_IES_L; //设置DIO0上升沿触发方式
|
||
DIO0_IE_L; //禁止DIO0中断
|
||
SX1276_TxPacket(cbuf,csize); //发送数据
|
||
while((!(DIO0_IFG&DIO0_BIT))&&j)j--; //等待GDIO0电平为高
|
||
DIO0_IFG_L; //清除中断标志位
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF进入接收状态
|
||
// 输入参数 : uint8_t cclen 可变数据包无效，固定数据包时为长度值
|
||
// 返回参数 : 无
|
||
// 说明 : 接收数据完成后DIO0从低电平变成高电平，
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_RXmode(uint8_t cclen)
|
||
{
|
||
Rx_mode(cclen); //RF接收机切换到RX模式
|
||
//SX_DIO0_DIR = 0; //做输入
|
||
DIO0_IFG_L; //清除DIO0标志位
|
||
DIO0_IES_L; //设置DIO0上升沿触发方式
|
||
DIO0_IE_H; //使能DIO0中断
|
||
}
|
||
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF进入Sleep状态
|
||
// 输入参数 : 无
|
||
// 返回参数 : 无
|
||
// 说明 : 无
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_SleepMode(void)
|
||
{
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write(REG_LR_IRQFLAGS,0xff);
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_SLEEP );
|
||
//P1OUT &= ~BIT4; //PA_TX 初始化输出为0
|
||
//P1OUT &= ~BIT5; //PA_TX 初始化输出为0 目的是降低待机功耗
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF CAD初始化
|
||
// 输入参数 : 无
|
||
// 返回参数 : 无
|
||
// 说明 : DIO1--CADDetected DIO3---CADDone
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_CADinit(void)
|
||
{
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_PREAMBLEMSB,0xf0);
|
||
SX1276Write( REG_LR_PREAMBLELSB,0xff);
|
||
SX1276Write( REG_LR_IRQFLAGSMASK,\
|
||
~(RFLR_IRQFLAGS_CADDONE|RFLR_IRQFLAGS_CADDETECTED));
|
||
//
|
||
SX1276Write( REG_LR_DIOMAPPING1,\
|
||
RFLR_DIOMAPPING1_DIO3_00 | RFLR_DIOMAPPING1_DIO1_10);
|
||
SX1276WriteRxTx(false); //set RF switch to RX path
|
||
SX1276Write(REG_LR_IRQFLAGS,0xff);
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF启动CAD，采样信道情况一次
|
||
// 输入参数 : 无
|
||
// 返回参数 : 无
|
||
// 说明 : 采样时间约为(2^SF+32)/BW
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_CAD_Sample(void)
|
||
{
|
||
SX1276WriteRxTx(false); //set RF switch to RX path
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_CAD );
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : WOR初始化
|
||
// 输入参数 : 无
|
||
// 返回参数 : 无
|
||
// 说明 : DIO1 :唤醒中断 DIO3：CAD超时中断（也可以认为是接收检测中断）
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_WORInit(void)
|
||
{
|
||
LSD_RF_CADinit(); //CAD功能初始化
|
||
//CADDone使能
|
||
//SX_DIO3_DIR=0; //做输入
|
||
DIO3_IFG_L; //清除DIO3标志位
|
||
DIO3_IES_L; //设置DIO3上升沿触发方式
|
||
DIO3_IE_H; //DIO3中断
|
||
//CADDetected使能
|
||
//SX_DIO1_DIR=0; //做输入
|
||
DIO1_IFG_L; //清除DIO1标志位
|
||
DIO1_IES_L; //设置DIO1上升沿触发方式
|
||
DIO1_IE_H; //使能DIO1中断
|
||
//关闭DIO0数据中断使能
|
||
DIO0_IE_L; //使能DIO0中断
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : 执行WOR操作
|
||
// 输入参数 : uint8_t cclen 0：进入睡眠。1：进入CAD检测模式
|
||
// 返回参数 : 无
|
||
// 说明 :
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_WOR_Execute(uint8_t cclen)
|
||
{
|
||
switch(cclen)
|
||
{
|
||
case 0: //启动睡眠
|
||
LSD_RF_SleepMode(); //进入睡眠模式
|
||
ON_Sleep_Timerout(); //启动睡眠超时定时器
|
||
break;
|
||
case 1: //进入CAD检测模式
|
||
OFF_Sleep_Timerout(); //关闭睡眠超时定时器
|
||
LSD_RF_CAD_Sample(); //启动CAD一次
|
||
|
||
break;
|
||
default: break;
|
||
}
|
||
}
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : WOR到RX
|
||
// 输入参数 : 无
|
||
// 返回参数 : 无
|
||
// 说明 : 退出WOR，进入RX模式，前导preamble仍然采用最大设置值。
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_WOR_Exit(uint8_t cclen)
|
||
{
|
||
OFF_Sleep_Timerout();
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_PAYLOADLENGTH,cclen);
|
||
SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_RXDONE));
|
||
SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_00 );
|
||
SX1276WriteRxTx(false); //set RF switch to RX path
|
||
SX1276Write( REG_LR_FIFOADDRPTR,0x00);
|
||
SX1276Write(REG_LR_IRQFLAGS,0xff);
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_RECEIVER );
|
||
//SX_DIO0_DIR = 0; //做输入
|
||
DIO0_IFG_L; //清除DIO0标志位
|
||
DIO0_IES_L; //设置DIO0上升沿触发方式
|
||
DIO0_IE_H; //使能DIO0中断
|
||
|
||
DIO1_IE_L; //禁止DIO1
|
||
DIO3_IE_L; //禁止DIO3
|
||
|
||
}
|
||
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
// 功能描述 : RF发送唤醒包
|
||
// 输入参数 : uint8_t*data：发送数据指针，uint8_t size发送数据长度
|
||
// 返回参数 : 无
|
||
// 说明 :
|
||
////////////////////////////////////////////////////////////////////////////////
|
||
void LSD_RF_Awake(uint8_t*cbuf,uint8_t csize)
|
||
{
|
||
//SX_DIO0_DIR = 0;
|
||
DIO0_IFG_L; //清除DIO0标志位
|
||
DIO0_IES_L; //设置DIO0上升沿触发方式
|
||
DIO0_IE_L; //禁止DIO0中断
|
||
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_PAYLOADLENGTH,csize);
|
||
SX1276WriteRxTx(true);
|
||
SX1276Write( REG_LR_FIFOADDRPTR,0x80);
|
||
SX1276WriteBuffer(REG_LR_FIFO,cbuf,csize);
|
||
SX1276Write(REG_LR_IRQFLAGS,0xff);
|
||
SX1276Write( REG_LR_IRQFLAGSMASK, ~(RFLR_IRQFLAGS_TXDONE));
|
||
SX1276Write( REG_LR_DIOMAPPING1, RFLR_DIOMAPPING1_DIO0_01 );
|
||
SX1276Write( REG_LR_PREAMBLEMSB,0x03);//set preamble length
|
||
SX1276Write( REG_LR_PREAMBLELSB,0xEC);//set preamble length
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_TRANSMITTER );
|
||
while((!DIO0_IFG)); //等待GDIO0电平为高
|
||
|
||
DIO0_IFG_L; //清除中断标志位
|
||
//发送完唤醒数据包后，将前导时间改回正常默认值。
|
||
SX1276Write( REG_LR_OPMODE, 0x80|RFLR_OPMODE_STANDBY );
|
||
SX1276Write( REG_LR_PREAMBLEMSB,0);//set preamble length
|
||
SX1276Write( REG_LR_PREAMBLELSB,10);//set preamble length
|
||
|
||
}
|
||
|
||
//*****************************************************************************************
|
||
#endif |